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FUJITSU SEMICONDUCTOR DATA SHEET
DS07-13703-1E
16-bit Proprietary Microcontroller
CMOS
F2MC-16LX MB90540/545 Series
MB90543/F543/549/F549/V540
s DESCRIPTION
The MB90540/545 series with FULL-CAN and FLASH ROM is specially designed for automotive and industrial applications. Its main features are two on board CAN Interfaces (one for MB90V545 series), which conform to V2.0 Part A and Part B, supporting very flexible message buffering. Thus, offering more functions than a normal full CAN approach. In the new 0.5m Technology Fujitsu now also offer FLASH-ROM. An internal voltage booster substitutes the necessity of a second programming voltage. An on board voltage regulator provides 3V to the internal MCU core. This constitutes a major advantage in terms of EMI and power consumption. The internal PLL clock frequency multiplier, provides an internal 62.5 nsec instruction cycle time with an external 4 MHz clock. Further more it features 4 channels Output Capture Units and 8 channels Input Capture Units with a 16-bit free running timer. Two UARTs constitute additional functionality for communication purposes. The external bus interface allows full use to be made of the 16MByte address space.
s FEATURES
* * * * * 16-bit core CPU : 4MHz external clock (16 MHz internal, 62.5 nsec instr. cycle time) 32 kHz Subsystem Clock New 0.5 m CMOS Process Technology Internal voltage regulator supports 3V MCU core, offering low EMI and low power consumption figures FULL-CAN interfaces (MB90540 series : 2 interf., MB90545 series : 1 interf.); conform to Version 2.0 Part A and Part B, flexible message buffering (mailbox and FIFO buffering can be mixed) (Continued)
s PACKAGE
100-pin Plastic QFP 100-pin Plastic LQFP
(FPT-100P-M06)
(FPT-100P-M05)
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MB90540/545 Series
(Continued) * Powerful interrupt functions (8 progr. priority levels; 8 external interrupts) * EI2OS - Automatic transfer function indep.of CPU * 18-bit Time-base counter * Watchdog Timer * 2 full duplex UARTs; UART0 supports 10.4 KBaud (USA standard), UART 1 also for serial transfer with clock (SCI) programmable * Serial I/O: 1ch for synchronous data transfer * A/D Converter: 8 ch. analog inputs (Resolution 10 bits or 8 bits) * 16-bit reload timer * 2ch * ICU (Input capture) 16bit * 8 ch * OCU (Output capture) 16bit * 4ch * 16-bit Programmable Pulse Generator 4ch * External bus interface * Optimized instruction set for controller applications (bit, byte, word and long-word data types; 23 different addressing modes; barrel shift; variety of pointers) * 4-byte instruction execution queue * signed multiply (16bit*16bit) and divide (32bit/16bit) instructions available * Program Patch Function * Fast Interrupt processing * Low Power Consumption - 10 different power saving modes: (Sleep, Stop, CPU intermittent mode, Hardware standby,...) * Package: 100-pin plastic QFP
Controller Area Network (CAN) - License of Robert Bosch GmbH
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MB90540/545 Series
s PRODUCT LINEUP
The following table provides a quick outlook of the MB90540/545 Series Features MB90V540 MB90F543/F549 CPU System clock ROM RAM F MC-16LX CPU On-chip PLL clock multiplier ( x 1, x 2, x 3, x 4, 1/2 when PLL stop) Minimum instruction execution time: 62.5 ns (4 MHz osc. PLL x 4) External 8 Kbytes Boot-block Flash memory 128 K/256 Kbytes 6 Kbytes Mask ROM 128 K/256 Kbytes 6 Kbytes 0.5 m CMOS with on-chip voltage regulator for internal power supply
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MB90543/549
Technology
0.5 m CMOS with on-chip volt0.5 m CMOS with on- age regulator for internal power chip voltage regulator supply + Flash memory On-chip for internal power supply charge pump for programming voltage 5 V10 % - 40 to 85 C PGA-256
Operating voltage range Temperature range Package
QFP100
UART0
Full duplex double buffer Supports asynchronous/synchronous (with start/stop bit) transfer Baud rate: 4808/5208/9615/10417/19230/38460/62500/500000 bps (asynchronous) 500K/1M/2Mbps (synchronous) at System clock = 16 MHz Full duplex double buffer Asynchronous (start-stop synchronized) and CLK-synchronous communication Baud rate: 1202/2404/4808/9615/31250 bps (asynchronous) 62.5K/12K/250K/500K/1 Mbps (synchronous) at 6,8,10,12,16 MHz Transfer can be started from MSB or LSB Supports internal clock synchronized transfer and external clock synchronized transfer Supports positive-edge and negative-edge clock synchronization Baud rate : 31.25K/62.5K/125K/500K/1Mbps at System clock = 16MHz 10-bit or 8-bit resolution 8 input channels Conversion time: 26.3 s (per one channel) Operation clock frequency: fsys/21, fsys/23, fsys/25 (fsys = System clock frequency) Supports External Event Count function Signals an interrupt when overflow Supports Timer Clear when a match with Output Compare(Channel 0) Operation clock freq.: fsys/22, fsys/24, fsys/26, fsys/28(fsys = System clock freq.) Signals an interrupt when a match with 16-bit IO Timer Four 16-bit compare registers A pair of compare registers can be used to generate an output signal
UART1(SCI)
Serial IO
A/D Converter 16-bit Reload Timer (2 channels) 16-bit IO Timer 16-bit Output Compare (4 channels)
(Continued)
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MB90540/545 Series
(Continued) Features
16-bit Input Capture (8 channels)
MB90V540
MB90F543/F549
MB90543/549
Rising edge, falling edge or rising & falling edge sensitive Four 16-bit Capture registers Signals an interrupt upon external event Supports 8-bit and 16-bit operation modes Eight 8-bit reload counters Eight 8-bit reload registers for L pulse width Eight 8-bit reload registers for H pulse width A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter 4 output pins Operation clock freq.: fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128s@fosc=4MHz (fsys = System clock frequency, fosc = Oscillation clock frequency) Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission responding to Remote Frame Prioritized 16 message buffers for data and ID's Supports multiple messages Flexible configuration of acceptance filtering: Full bit compare / Full bit mask / Two partial bit masks Supports up to 1Mbps Sub-clock for low power operation Can be programmed edge sensitive or level sensitive Virtually all external pins can be used as general purpose IO All push-pull outputs and schmitt trigger inputs Bit-wise programmable as input/output or peripheral signal Supports automatic programming, Embedded AlgorithmTM *1 Write/Erase/Erase-Suspend/ Resume commands A flag indicating completion of the algorithm Number of erase cycles: 10,000 times Data retention time: 10 years Flash Writer from Minato Electronics Inc. Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature: protects the content of the Flash memory
8/16-bit Programmable Pulse Generator (4 channels)
CAN Interface 540 series: 2 channels 545 series: 1 channel 32 kHz Subclock External Interrupt (8 channels) IO Ports
Flash Memory
*1: Embedded Algorithm is a trade mark of Advanced Micro Devices Inc.
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MB90540/545 Series
s PIN ASSIGNMENT
(Top view)
P14/AD12 P13/AD11 P12/AD10 P11/AD09 P10/AD08 P07/AD07 P06/AD06 P05/AD05 P04/AD04 P03/AD03 P02/AD02 P01/AD01 P17/AD15 P16/AD14 P15/AD13 P00/AD00
Vcc
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 P26/A22 P27/A23 P30/ALE P31/RD Vss P32/WRL/WR P33/WRH P34/HRQ P35/HAK P36/RDY P37/CLK P40/SOT0 P41/SCK0 P42/SIN0 P43/SIN1 P44/SCK1 Vcc P45/SOT1 P46/SOT2 P47/SCK2 C P50/SIN2 P51/INT4 P52/INT5
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
Vss
X1
X0
X0A X1A PA0 RST P97/RX1 P96/TX1 P95/RX0 P94/TX0 P93/INT3 P92/INT2 P91/INT1 P90/INT0 P87/TOT1 P86/TIN1 P85/OUT1 P84/OUT0 P83/PPG3 P82/PPG2 P81/PPG1 P80/PPG0 P77/OUT3/IN7 P76/OUT2/IN6 P75/IN5 P74/IN4 P73/IN3 P72/IN2 P71/IN1 P70/IN0 HST MD2
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48 P57/TOT0
49 MD0
P55/ADTG
P60/AN0
P61/AN1
P62/AN2
P63/AN3
Vss
P64/AN4
P54/INT7
P65/AN5
AVR+
AVR-
AVcc
AVss
P66/AN6
P67/AN7
P53/INT6
(FPT-100P-M06)
P56/TIN0
MD1
50
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MB90540/545 Series
s PIN DESCRIPTION
No. 82 83 80 79 77 52 Pin name X0 X1 X0A X1A RST HST P00 to P07 85 to 92 AD00 to AD07 P10 to P17 93 to 100 AD08 to AD15 P20 to P27 1 to 8 A16 to A23 P30 9 ALE P31 10 RD P32 WRL 12 WR I I I H I I Circuit type A (Oscillation) A (Oscillation) B C Function High speed oscillator input pins Low speed oscillator input pins External reset request input Hardware standby input General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. I/O pins for 8 higher bits of the external address/data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. Output pins for A16 to A23 ot the external address bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. Address latch enable output pin. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode. Read strobe output pin for the data bus. This function is enabled when the external bus is enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the WR/WRL pin output is disabled. Write strobe output pin for the data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to write-strobe 8 bits of the data bus in 8-bit access. General I/O port with programmable pullup. This function is enabled in the single-chip mode or external bus 8-bit mode or when WRH pin output is disabled. I WRH Write strobe output pin for the 8 higher bits of the data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled.
P33 13
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MB90540/545 Series
No. Pin name P34 14 HRQ P35 15 HAK I I Circuit type Function General I/O port with programmable pullup. This function is enabled in the single-chip mode or when hold function is disabled. Hold request input pin. This function is enabled when both the external bus and the hold function are enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when hold function is disabled. Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the external ready function is disabled. Ready input pin. This function is enabled when both the external bus and the external ready function are enabled. General I/O port with programmable pullup. This function is enabled in the single-chip mode or when the clock output is disabled. CLK output pin. This function is enabled when both the external bus and CLK output are enabled. General I/O port. This function is enabled when UART0 disables serial data output. Serial data output pin for UART0. This function is enabled when UART0 enables serial data output. General I/O port. This function is enabled when UART0 disables clock output. Clock I/O pin for UART0. This function is enabled when UART0 enables clock output. General I/O port. This function is always enabled. G Serial data input pin for UART0. While UART0 is operating for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is always enabled. G Serial data input pin for UART1. While UART1 is operating for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is enabled when UART1 disables clock output. Clock pulse input/output pin for UART1. This function is enabled when UART1 enables clock output. General I/O port. This function is enabled when UART1 disables serial data output. Serial data output pin for UART1. This function is enabled when UART1 enables serial data output.
P36 16 RDY P37 17 CLK P40 18 SOT0 P41 19 SCK0 P42 20 SIN0 P43 21 SIN1 G G H I
P44 22 SCK1 P45 24 SOT1 G G
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MB90540/545 Series
No. Pin name P46 25 SOT2 P47 26 SCK2 P50 28 D G G Circuit type Function General I/O port. This function is enabled when the Serial IO disables serial data output. Serial data output pin for the Serial IO. This function is enabled when the Serial IO enables serial data output. General I/O port. This function is enabled when the Serial IO disables clock output. Clock pulse input/output pin for the Serial IO. This function is enabled when the Serial IO enables clock output. General I/O port. This function is always enabled. Serial data input pin for the Serial IO. While the Serial IO is operating for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is always enabled. D External interrupt request input pins for INT4 to INT7. While external interrupt is allowed, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is always enabled. D Trigger input pin for the A/D converter. While the A/D converter is operating for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. The function is enabled when the analog input enable register specifies port. Analog input pins for the A/D converter. This function is enabled when the analog input enable register specifies AD. General I/O port. The function is enabled when the analog input enable register specifies port. Analog input pins for the A/D converter. This function is enabled when the analog input enable register specifies AD. General I/O port. This function is always enabled. D Event input pin for the reload timers 0. While the reload timer is operating for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is enabled when the reload timers 0 disables output. Output pin for the reload timers 0. This function is enabled when the reload timers 0 enables output.
SIN2
P51 to P54 29 to 32
INT4 to INT7
P55 33
ADTG
P60 to P63 38 to 41 AN0 to AN3 P64 to P67 43 to 46 AN4 to AN7 P56 47 E E
TIN0
P57 48 TOT0 D
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MB90540/545 Series
No. Pin name P70 to P75 53 to 58 D Circuit type Function General I/O ports. This function is always enabled. Data sample input pins for input captures ICU0 to ICU5. While the ICU is for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O ports. This function is enabled when the OCU disables waveform output. Waveform output pins for output compares OCU2 and OCU3. This function is enabled when the OCU enables waveform output. Data sample input pin for input captures ICU6 and ICU7. While the ICU is for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O ports. This function is enabled when PPG disables waveform output. Output pins for PPGs. This function is enabled when PPG enables waveform output. General I/O ports. This function is enabled when the OCU disables waveform output. Waveform output pins for output compares OCU0 and OCU1. This function is enabled when the OCU enables waveform output. General I/O port. This function is always enabled. D Event input pin for the reload timers 1. While the reload timer is operating for input, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is enabled when the reload timers 0 disables output. Output pin for the reload timers 1 This function is enabled when the reload timers 1 enables output. General I/O port. This function is always enabled. D External interrupt request input pins for INT0 to INT3. While external interrupt is allowed, the input of the pin is used as required. Except when the function is intentionally used, output from the other functions must be stopped. General I/O port. This function is enabled when CAN0 disables output. TX Output pin for CAN0. This function is enabled when CAN0 enables output. General I/O port. This function is always enabled. D RX input pin for CAN0 Interface. When the CAN function is used, output from the other functions must be stopped.
IN0 to IN5
P76 to P77 OUT2 to OUT3 59 to 60 IN6 to IN7 D
P80 to P83 61 to 64 PPG0 to PPG3 P84 to P85 65 to 66 OUT0 to OUT1 P86 67 D D
TIN1
P87 68 TOT1 P90 to P93 69 to 72 D
INT0 to INT3
P94 73 TX0 P95 74 RX0 D
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MB90540/545 Series
No. Pin name P96 75 TX1 P97 76 RX1 PA0 AVCC AVSS AVR+ AVRMD0 MD1 MD2 C VCC VSS D D Circuit type Function General I/O port. This function is enabled when CAN1 disables output. TX Output pin for CAN1. This function is enabled when CAN1 enables output (only MB90540 series). General I/O port. This function is always enabled. RX input pin for CAN1 Interface. When the CAN function is used, output from the other functions must be stopped (only MB90540 series). General I/O port. This function is always enabled.
78 34 37 35 36 49 50 51 27 23; 84 11; 42 81
D
Power supply for the A/D Converter. This power supply must be Power supply turned on or off while a voltage higher than or equal to AVcc is applied to Vcc. Power supply Dedicated ground pin for the A/D Converter Reference voltage input for the A/D Converter. This power supply Power supply must be turned on or off while a voltage higher than or equal to AVR+ is applied to AVcc. Power supply Lower reference voltage input for the A/D Converter C F Input pins for specifying the operating mode. The pins must be directly connected to Vcc or Vss. Input pin for specifying the operating mode. The pin must be directly connected to Vcc or Vss. This is the power supply stabilization capacitor pin. It should be connected externally to an 0.1 F ceramic capacitor. Power supply Power supply for digital circuits Power supply Ground for digital circuits
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MB90540/545 Series
s I/O CIRCUIT TYPE
Circuit type X1 Diagram Remarks * Oscillation feedback resistor: 1 M approx.
X0 A
Standby control signal
* Hysteresis input with pull-up Resistor: 50 k approx. B R R HYS
* Hysteresis input C R HYS
VCC P-ch
* CMOS output * Hysteresis input
D
N-ch
R
HYS
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MB90540/545 Series
Circuit type Diagram
VCC P-ch
Remarks * CMOS output * Hysteresis input * Analog input
N-ch
E
Analog input R HYS
R F R
HYS
* Hysteresis input * Pull-down Resistor: 50 k approx. (except FLASH devices)
VCC P-ch
* CMOS output * Hysteresis input * TTL input (FLASH devices only)
N-ch
G
R R T
HYS
TTL
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MB90540/545 Series
Circuit type Diagram Remarks * CMOS output * Hysteresis input * Programmable pullup resistor: 50 k approx.
VCC
CNTL
VCC P-ch
H
N-ch
R
HYS
VCC
CNTL
VCC P-ch
* * * *
CMOS output Hysteresis input TTL input (FLASH devices only) Programmable pullup resistor: 50 k approx.
N-ch
I
R R T
HYS TTL
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MB90540/545 Series
s HANDLING DEVICES
(1) Preventing latch-up CMOS IC chips may suffer latch-up under the following conditions: * A voltage higher than Vcc or lower than Vss is applied to an input or output pin. * A voltage higher than the rated voltage is applied between Vcc and Vss. * The AVcc power supply is applied before the Vcc voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. (2) Handling unused input pins Do not leave unused input pins open, as doing so may cause misoperation of the device. Use a pull-up or pulldown resistor. (3) Using external clock To use external clock, drive the X0 and X1 pins in reverse phase. Below is a diagram of how to use external clock. MB90540/545 Series X0 X1
Using external clock (4) Power supply pins (Vcc/Vss) Ensure that all Vcc-level power supply pins are at the same potential. In addition, ensure the same for all Vsslevel power supply pins. (See the figure below.) If there are more than one Vcc or Vss system, the device may operate incorrectly even within the guaranteed operating range. Vcc Vss
Vcc Vss Vcc
Vss
MB90540/545 Vcc Series
Vss
Vss
Vcc
(5) Pull-up/down resistors The MB90540/545 Series does not support internal pull-up/down resistors(except Port0 - Port3:pull-up resistors). Use external components where needed. 14
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MB90540/545 Series
(6) Crystal Oscillator Circuit Noises around X0 or X1 pins may be possible causes of abnormal operations. Make sure to provide bypass capacitors via shortest distance from X0, X1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0 and X1 pins with an grand area for stabilizing the operation. (7) Turning-on Sequence of Power Supply to A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply(AVCC, AVR + , AVR - ) and analog inputs (AN0 to AN7) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage not exceed AVR + or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). (8) Connection of Unused Pins of A/D Converter Connect unused pins of A/D converter to AVCC = VCC, AVSS = AVR + = VSS. (9) N.C. Pin The N.C. (internally connected) pin must be opened for use. (10) Notes on Energization To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during energization at 50 or more ms (0.2 V to 2.7 V). (11) Initialization In the device, there are internal registers which is initialized only by a power-on reset. To initialize these registers turning on the power again. (12) Directions of "DIV A, Ri" and "DIVW A, RWi" instructions In the Signed multiplication and division instructions ("DIV A, Ri" and "DIVW A, RWi"), the value of the corresponding bank register (DTB, ADB, USB, SSB) is set in "00h". If the values of the corresponding bank register (DTB,ADB,USB,SSB) are setting other than "00h", the remainder by the execution result of the instruction is not stored in the register of the instruction operand.
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MB90540/545 Series
s BLOCK DIAGRAM
X0,X1 X0A,X1A RSTX HSTX IO Timer Input Capture 8 ch.
ROM 128 KB /256 KB
Clock Controller
16LX CPU
RAM 6 KB
IN[5:0] IN[7:6]/OUT[3:2]
Output Compare 4 ch.
OUT[1:0]
Prescaler
SOT0 SCK0 SIN0
UART0
8/16-bit PPG 4 ch.
PPG[3:0]
Prescaler
CAN Controller
RX[1:0]* TX[1:0]*
SOT1 SCK1 SIN1
UART1 (SCI)
16-bit Reload Timer 2 ch.
TIN[1:0] TOT[1:0]
Prescaler
FMC-16 Bus
AD[15:00] A[23:16] ALE RD External Bus Interface WRL WRH HRQ HAK RDY CLK
SCK2 SOT2 SIN2 AVCC AVSS AN[7:0] AVR+ AVRADTG
Serial I/O
10-bit ADC 8 ch.
External Interrupt
INT[7:0]
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MB90540/545 Series
s MEMORY SPACE
The memory space of the MB90540/545 Series is shown below MB90V540 FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) External 00FFFFH 004000H 003FFFH 003900H External 0020FFH 001FF5H 001FF0H ROM (Image of FF bank) Peripheral 003900H 002000H 0018FFH RAM 6K RAM 8K 000100H External 0000BFH 000000H Peripheral 0000BFH 000000H 000100H External Peripheral 0000BFH 000000H 000100H External Peripheral External 00FFFFH 004000H 003FFFH ROM (Image of FF bank) Peripheral 003900H 002000H 0018FFH RAM 6K External 00FFFFH 004000H 003FFFH External FFFFFFH FF0000H FEFFFFH FE0000H MB90543/F543 ROM (FF bank) ROM (FE bank) FFFFFFH FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H MB90549/F549 ROM (FF bank) ROM (FE bank) ROM (FD bank) ROM (FC bank) External ROM (Image of FF bank) Peripheral
ROM correction
Memory space map The high-order portion of bank 00 gives the image of the FF bank ROM to make the small model of the C compiler effective. Since the low-order 16 bits are the same, the table in ROM can be referenced without using the far specification in the pointer declaration. For example, an attempt to access 00C000H accesses the value at FFC000H in ROM. The ROM area in bank FF exceeds 48 Kbytes, and its entire image cannot be shown in bank 00. The image between FF4000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF3FFFH is visible only in bank FF.
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MB90540/545 Series
s I/O MAP
Address 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH to 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H Port 0 direction register Port 1 direction register Port 2 direction register Port 3 direction register Port 4 direction register Port 5 direction register Port 6 direction register Port 7 direction register Port 8 direction register Port 9 direction register Port A direction register Analog Input Enable Port 0 Pullup control register Port 1 Pullup control register Port 2 Pullup control register Port 3 Pullup control register Serial Mode Control Register 0 Status Register 0 Input/Output Data Register 0 Rate and Data Register 0 Register Port 0 data register Port 1 data register Port 2 data register Port 3 data register Port 4 data register Port 5 data register Port 6 data register Port 7 data register Port 8 data register Port 9 data register Port A data register Abbreviation Access PDR0 PDR1 PDR2 PDR3 PDR4 PDR5 PDR6 PDR7 PDR8 PDR9 PDRA Reserved DDR0 DDR1 DDR2 DDR3 DDR4 DDR5 DDR6 DDR7 DDR8 DDR9 DDRA ADER PUCR0 PUCR1 PUCR2 PUCR3 UMC0 USR0 UIDR0/ UODR0 URD0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W UART0 Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Port 6, A/D Port 0 Port 1 Port 2 Port 3 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _0B 1 1 1 1 1 1 1 1B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B 0 0 0 1 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0XB R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Pripheral Port 0 Port 1 Port 2 Port 3 Port 4 Port 5 Port 6 Port 7 Port 8 Port 9 Port A Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB _ _ _ _ _ _ _XB
(Continued)
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MB90540/545 Series
Address 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H 34H 35H 36H 37H 38H 39H 3AH 3BH 3CH 3DH 3EH 3FH 40H 41H 42H 43H 44H 45H 46H
PPG6 operation mode control register PPG7 operation mode control register PPG4 operation mode control register PPG5 operation mode control register PPG2 operation mode control register PPG3 operation mode control register
Register Serial Mode Register 1 Serial Control Register 1 Input/Output Data Register 1 Serial Status Register 1 UART1 Prescaler Control Register Edge Selector Serial IO Prescaler Serial Mode Control Serial Mode Control Serial Data Edge Selector External Interrupt Enable External Interrupt Request External Interrupt Level External Interrupt Level A/D Control Status 0 A/D Control Status 1 A/D Data 0 A/D Data 1
PPG0 operation mode control register PPG1 operation mode control register
Abbreviation Access SMR1 SCR1 SIDR1/ SODR1 SSR1 U1CDCR SES1 Reserved SCDCR SMCS SMCS SDR SES2 ENIR EIRR ELVR ELVR ADCS0 ADCS1 ADCR0 ADCR1 PPGC0 PPGC1 PPG01 Reserved PPGC2 PPGC3 PPG23 Reserved PPGC4 PPGC5 PPG45 Reserved PPGC6 PPGC7 PPG67 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value 0 0 0 0 0 0 0 0B 0 0 0 0 0 1 0 0B
UART1
XXXXXXXXB 0 0 0 0 1_0 0B 0_ _ _1 1 1 1B _ _ _ _ _ _ _0B 0_ _ _1 1 1 1B _ _ _ _0 0 0 0B
Serial IO
0 0 0 0 0 0 1 0B XXXXXXXXB _ _ _ _ _ _ _0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B XXXXXXXXB 0 0 0 0 1 _ XXB 0 _ 0 0 0 _ _ 1B
External Interrupt
A/D Converter
PPG0 and PPG1 clock select register
16-bit Programable Pulse 0 _ 0 0 0 0 0 1B Generator 0/1
0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _1B
PPG2 and PPG3 clock select register
16-bit Programable Pulse 0 _ 0 0 0 0 0 1B Generator 2/3
0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B
PPG4 and PPG5 clock select register
16-bit Programable Pulse 0 _ 0 0 0 0 0 1B Generator 4/5
0 0 0 0 0 0 _ _B 0 _ 0 0 0 _ _ 1B
PPG6 and PPG7 clock select register
16-bit Programable Pulse 0 _ 0 0 0 0 0 1B Generator 6/7
0 0 0 0 0 0 _ _B
(Continued)
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MB90540/545 Series
Address 47H to 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 53H 54H 55H 56H 57H 58H 59H 5AH 5BH 5CH to 6BH 6CH 6DH 6EH 6FH 70H to 7FH 80H to 8F H 90H to 9D H 9EH 9FH A0H A1H A2H to A4H ROM Correction Control Status Delayed Interrupt/release Low-power Mode Clock Selector Timer Data Timer Data Timer Control ROM Mirror Input Capture Control Status 0/1 Input Capture Control Status 2/3 Input Capture Control Status 4/5 Input Capture Control Status 6/7 Timer Control Status 0 Timer Control Status 0 Timer 0/Reload 0 Timer 0/Reload 0 Timer Control Status 1 Timer Control Status 1 Timer 1/Reload 1 Timer 1/Reload 1 Output Compare Control Status 0 Output Compare Control Status 1 Output Compare Control Status 2 Output Compare Control Status 3 Register Abbreviation Access Reserved ICS01 ICS23 ICS45 ICS67 TMCSR0 TMCSR0 TMR0/ TMRLR0 TMR0/ TMRLR0 TMCSR1 TMCSR1 TMR1/ TMRLR1 TMR1/ TMRLR1 OCS0 OCS1 OCS2 OCS3 Reserved TCDT TCDT TCCS ROMM R/W R/W R/W R/W ROM Mirror I/O Timer 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ _ _ _ 1B R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 16-bit Reload Timer 1 16-bit Reload Timer 0 Input Capture 0/1 0 0 0 0 0 0 0 0B Input Capture 2/3 0 0 0 0 0 0 0 0B Input Capture 4/5 0 0 0 0 0 0 0 0B Input Capture 6/7 0 0 0 0 0 0 0 0B 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB 0 0 0 0 0 0 0 0B _ _ _ _ 0 0 0 0B XXXXXXXXB XXXXXXXXB Output Compare 0 0 0 0 _ _ 0 0B 0/1 _ _ _0 0 0 0 0B Output Compare 0 0 0 0 _ _ 0 0B 2/3 _ _ _ 0 0 0 0 0B Peripheral Initial value
Reserved for CAN 0 Interface . Refer to "CAN Controller Hardware Manual" Reserved for CAN 1 Interface . Refer to "CAN Controller Hardware Manual" Reserved PACSR DIRR LPMCR CKSCR Reserved R/W R/W R/W R/W ROM Correction 0 0 0 0 0 0 0 0B Delayed Interrupt _ _ _ _ _ _ _ 0B Low Power Controller Low Power Controller 0 0 0 1 1 0 0 0B 1 1 1 1 1 1 0 0B
(Continued)
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MB90540/545 Series
(Continued) Address
A5H A6H A7H A8H A9H AAH ABH to ADH AEH AFH B0H B1H B2H B3H B4H B5H B6H B7H B8H B9H BAH BBH BCH BDH BEH BFH COH to FF H Interrupt control register 00 Interrupt control register 01 Interrupt control register 02 Interrupt control register 03 Interrupt control register 04 Interrupt control register 05 Interrupt control register 06 Interrupt control register 07 Interrupt control register 08 Interrupt control register 09 Interrupt control register 10 Interrupt control register 11 Interrupt control register 12 Interrupt control register 13 Interrupt control register 14 Interrupt control register 15 Flash Control Status (Flash only, otherwise reserved)
Register Automatic ready function select reg. External address output control reg. Bus control signal select register Watchdog Control Time Base Timer Control Watch timer control register
Abbreviation Access ARSR HACR ECSR WDTC TBTC WTC Reserved FMCS Reserved ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 External R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W W W W R/W R/W R/W
Peripheral
Initial value
0 0 1 1 _ _ 0 0B External Memory 0 0 0 0 0 0 0 0B Access 0 0 0 0 0 0 0 _B Watchdog Timer Watch Timer XXXXX 1 1 1B 1 X 0 0 0 0 0 0B Time Base Timer 1 - - 0 0 1 0 0B
Flash Memory
0 0 0 X 0 _ _ 0B
0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B Interrupt controller 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B 0 0 0 0 0 1 1 1B
Address 1FF0H 1FF1H 1FF2H 1FF3H 1FF4H 1FF5H
Register ROM Correction Address 0 ROM Correction Address 1 ROM Correction Address 2 ROM Correction Address 3 ROM Correction Address 4 ROM Correction Address 5
Abbreviation Access PADR0 PADR0 PADR0 PADR1 PADR1 PADR1 R/W R/W R/W R/W R/W R/W
Peripheral
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
ROM Correction
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MB90540/545 Series
Address 3900H 3901H 3902H 3903H 3904H 3905H 3906H 3907H 3908H 3909H 390AH 390BH 390CH 390DH 390EH 390FH 3910H to 3917H 3918H 3919H 391AH 391BH 391CH 391DH 391EH 391FH 3920H 3921H 3922H 3923H 3924H 3925H 3926H 3927H
Register Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Reload L Reload H Input Capture 0 Input Capture 0 Input Capture 1 Input Capture 1 Input Capture 2 Input Capture 2 Input Capture 3 Input Capture 3 Input Capture 4 Input Capture 4 Input Capture 5 Input Capture 5 Input Capture 6 Input Capture 6 Input Capture 7 Input Capture 7
Abbreviation Access PRLL0 PRLH0 PRLL1 PRLH1 PRLL2 PRLH2 PRLL3 PRLH3 PRLL4 PRLH4 PRLL5 PRLH5 PRLL6 PRLH6 PRLL7 PRLH7 IPCP0 IPCP0 IPCP1 IPCP1 IPCP2 IPCP2 IPCP3 IPCP3 IPCP4 IPCP4 IPCP5 IPCP5 IPCP6 IPCP6 IPCP7 IPCP7 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R R R R R R R R R R R R R R R R
Peripheral 16-bit Programable Pulse Generator 0/1
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 2/3
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 4/5
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
16-bit Programable Pulse Generator 6/7
XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Reserved XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Captue 2/3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Captue 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Input Captue 6/7 XXXXXXXXB XXXXXXXXB XXXXXXXXB
Input Captue 0/1
(Continued)
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MB90540/545 Series
(Continued) Address
3928H 3929H 392AH 392BH 392CH 392DH 392EH 392FH 3930H to 39FFH 3A00H to 3AFFH 3B00H to 3BFFH 3C00H to 3CFFH 3D00H to 3DFFH 3E00H to 3FFFH Note
Register Output Compare 0 Output Compare 0 Output Compare 1 Output Compare 1 Output Compare 2 Output Compare 2 Output Compare 3 Output Compare 3
Abbreviation Access OCCP0 OCCP0 OCCP1 OCCP1 OCCP2 OCCP2 OCCP3 OCCP3 R/W R/W R/W R/W R/W R/W R/W R/W
Peripheral
Initial value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB
Output Compare 0/1
Output Compare 2/3
Reserved Reserved for CAN 0 Interface. Refer to "CAN Controller Hardware Manual" Reserved for CAN 0 Interface. Refer to "CAN Controller Hardware Manual" Reserved for CAN 1 Interface. Refer to "CAN Controller Hardware Manual" Reserved for CAN 1 Interface. Refer to "CAN Controller Hardware Manual" Reserved
Initial value of "_" represents unused bit, "X" represents unknown value. Addresses in the range 0000H to 00FFH, which are not listed in the table, are reserved for the primary functions of the MCU. A read access to these reserved addresses results reading "X" and any write access should not be performed.
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MB90540/545 Series
s CAN CONTROLLER
The MB90540 series contains two CAN controller (CAN0 and CAN1), the MB90545 series contains only one (CAN0 ). The Evaluation Chip MB90V540 also has two CAN controller. The CAN controller has the following features: * Conforms to CAN Specification Version 2.0 Part A and B - Supports transmission/reception in standard frame and extended frame formats * Supports transmitting of data frames by receiving remote frames * 16 transmitting/receiving message buffers - 29-bit ID and 8-byte data - Multi-level message buffer configuration * Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as 1D acceptance mask - Two acceptance mask registers in either standard frame format or extended frame formats * Bit rate programmable from 10 Kbits/s to 1 Mbits/s (when input clock is at 16 MHz) List of Control Registers Address CAN0 000070H 000071H 000072H 000073H 000074H 000075H 000076H 000077H 000078H 000079H 00007AH 00007BH 00007CH 00007DH 00007EH 00007FH CAN1 000080H 000081H 000082H 000083H 000084H 000085H 000086H 000087H 000088H 000089H 00008AH 00008BH 00008CH 00008DH 00008EH 00008FH Register Message buffer valid register Transmit request register Transmit cancel register Transmit complete register Receive complete register Remote request receiving register Receive overrun register Receive interrupt enable register Abbreviation BVALR TREQR TCANR TCR RCR RRTRR ROVRR RIER Access R/W R/W W R/W R/W R/W R/W R/W Initial Value 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B 00000000 00000000B
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MB90540/545 Series
List of Control Registers Address CAN0 003B00H 003B01H 003B02H 003B03H 003B04H 003B05H 003B06H 003B07H 003B08H 003B09H 003B0AH 003B0BH 003B0CH 003B0DH 003B0EH 003B0FH 003B10H 003B11H 003B12H 003B13H 003B14H 003B15H 003B16H 003B17H 003B18H 003B19H 003B1AH 003B1BH CAN1 003D00H 003D01H 003D02H 003D03H 003D04H 003D05H 003D06H 003D07H 003D08H 003D09H 003D0AH 003D0BH 003D0CH 003D0DH 003D0EH 003D0FH 003D10H 003D11H 003D12H 003D13H 003D14H 003D15H 003D16H 003D17H 003D18H 003D19H 003D1AH 003D1BH Acceptance mask register 1 AMR1 R/W XXXXX--- XXXXXXXXB Acceptance mask register 0 AMR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Acceptance mask select register AMSR R/W XXXXXXXX XXXXXXXXB XXXXXXXX XXXXXXXXB Register Control status register Last event indicator register Receive/transmit error counter Bit timing register IDE register Transmit RTR register Remote frame receive waiting register Transmit interrupt enable register Abbreviation Access CSR LEIR RTEC BTR IDER TRTRR RFWTR TIER R/W, R R/W R R/W R/W R/W R/W R/W Initial Value 00---000 0----0-1B -------- 000-0000B 00000000 00000000B -1111111 11111111B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB 00000000 00000000B XXXXXXXX XXXXXXXXB
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MB90540/545 Series
List of Message Buffers (ID Registers) (1) Address CAN0 003A00H to 003A1FH 003A20H 003A21H 003A22H 003A23H 003A24H 003A25H 003A26H 003A27H 003A28H 003A29H 003A2AH 003A2BH 003A2CH 003A2DH 003A2EH 003A2FH 003A30H 003A31H 003A32H 003A33H 003A34H 003A35H 003A36H 003A37H 003A38H 003A39H 003A3AH 003A3BH CAN1 003C00H to 003C1FH 003C20H 003C21H 003C22H 003C23H 003C24H 003C25H 003C26H 003C27H 003C28H 003C29H 003C2AH 003C2BH 003C2CH 003C2DH 003C2EH 003C2FH 003C30H 003C31H 003C32H 003C33H 003C34H 003C35H 003C36H 003C37H 003C38H 003C39H 003C3AH 003C3BH ID register 6 IDR6 R/W XXXXX--- XXXXXXXXB ID register 5 IDR5 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 4 IDR4 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 3 IDR3 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 2 IDR2 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 1 IDR1 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 0 IDR0 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXX XXXXXXXXB
General-purpose RAM
R/W
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MB90540/545 Series
List of Message Buffers (ID Registers) (2) Address CAN0 003A3CH 003A3DH 003A3EH 003A3FH 003A40H 003A41H 003A42H 003A43H 003A44H 003A45H 003A46H 003A47H 003A48H 003A49H 003A4AH 003A4BH 003A4CH 003A4DH 003A4EH 003A4FH 003A50H 003A51H 003A52H 003A53H 003A54H 003A55H 003A56H 003A57H 003A58H 003A59H 003A5AH 003A5BH 003A5CH 003A5DH 003A5EH 003A5FH CAN1 003C3CH 003C3DH 003C3EH 003C3FH 003C40H 003C41H 003C42H 003C43H 003C44H 003C45H 003C46H 003C47H 003C48H 003C49H 003C4AH 003C4BH 003C4CH 003C4DH 003C4EH 003C4FH 003C50H 003C51H 003C52H 003C53H 003C54H 003C55H 003C56H 003C57H 003C58H 003C59H 003C5AH 003C5BH 003C5CH 003C5DH 003C5EH 003C5FH ID register 15 IDR15 R/W XXXXX--- XXXXXXXXB ID register 14 IDR14 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 13 IDR13 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 12 IDR12 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 11 IDR11 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 10 IDR10 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 9 IDR9 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 8 IDR8 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB ID register 7 IDR7 R/W XXXXX--- XXXXXXXXB XXXXXXXX XXXXXXXXB Register Abbreviation Access Initial Value XXXXXXXX XXXXXXXXB
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MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (1) Address CAN0 003A60H 003A61H 003A62H 003A63H 003A64H 003A65H 003A66H 003A67H 003A68H 003A69H 003A6AH 003A6BH 003A6CH 003A6DH 003A6EH 003A6FH CAN1 003C60H 003C61H 003C62H 003C63H 003C64H 003C65H 003C66H 003C67H 003C68H 003C69H 003C6AH 003C6BH 003C6CH 003C6DH 003C6EH 003C6FH Register DLC register 0 DLC register 1 DLC register 2 DLC register 3 DLC register 4 DLC register 5 DLC register 6 DLC register 7 Abbreviation Access DLCR0 DLCR1 DLCR2 DLCR3 DLCR4 DLCR5 DLCR6 DLCR7 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB
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MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (2) Address CAN0 003A70H 003A71H 003A72H 003A73H 003A74H 003A75H 003A76H 003A77H 003A78H 003A79H 003A7AH 003A7BH 003A7CH 003A7DH 003A7EH 003A7FH 003A80H to 003A87H 003A88H to 003A8FH 003A90H to 003A97H 003A98H to 003A9FH 003AA0H to 003AA7H 003AA8H to 003AAFH 003AB0H to 003AB7H CAN1 003C70H 003C71H 003C72H 003C73H 003C74H 003C75H 003C76H 003C77H 003C78H 003C79H 003C7AH 003C7BH 003C7CH 003C7DH 003C7EH 003C7FH 003C80H to 003C87H 003C88H to 003C8FH 003C90H to 003C97H 003C98H to 003C9FH 003CA0H to 003CA7H 003CA8H to 003CAFH 003CB0H to 003CB7H Register DLC register 8 DLC register 9 DLC register 10 DLC register 11 DLC register 12 DLC register 13 DLC register 14 DLC register 15 Abbreviation Access DLCR8 DLCR9 DLCR10 DLCR11 DLCR12 DLCR13 DLCR14 DLCR15 R/W R/W R/W R/W R/W R/W R/W R/W Initial Value ----XXXX ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB ----XXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
Data register 0 (8 bytes)
DTR0
R/W
Data register 1 (8 bytes)
DTR1
R/W
Data register 2 (8 bytes)
DTR2
R/W
Data register 3 (8 bytes)
DTR3
R/W
Data register 4 (8 bytes)
DTR4
R/W
Data register 5 (8 bytes)
DTR5
R/W
Data register 6 (8 bytes)
DTR6
R/W
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MB90540/545 Series
List of Message Buffers (DLC Registers and Data Registers) (3) Address CAN0 003AB8H to 003ABFH 003AC0H to 003AC7H 003AC8H to 003ACFH 003AD0H to 003AD7H 003AD8H to 003ADFH 003AE0H to 003AE7H 003AE8H to 003AEFH 003AF0H to 003AF7H 003AF8H to 003AFFH CAN1 003CB8H to 003CBFH 003CC0H to 003CC7H 003CC8H to 003CCFH 003CD0H to 003CD7H 003CD8H to 003CDFH 003CE0H to 003CE7H 003CE8H to 003CEFH 003CF0H to 003CF7H 003CF8H to 003CFFH Register Abbreviation Access Initial Value XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB XXXXXXXXB to XXXXXXXXB
Data register 7 (8 bytes)
DTR7
R/W
Data register 8 (8 bytes)
DTR8
R/W
Data register 9 (8 bytes)
DTR9
R/W
Data register 10 (8 bytes)
DTR10
R/W
Data register 11 (8 bytes)
DTR11
R/W
Data register 12 (8 bytes)
DTR12
R/W
Data register 13 (8 bytes)
DTR13
R/W
Data register 14 (8 bytes)
DTR14
R/W
Data register 15 (8 bytes)
DTR15
R/W
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MB90540/545 Series
s INTERRUPT MAP
Interrupt cause Reset INT9 instruction Exception CAN 0 RX CAN 0 TX/NS CAN 1 RX CAN 1 TX/NS External Interrupt INT0/INT1 Time Base Timer 16-bit Reload Timer 0 A/D Converter I/O Timer External Interrupt INT2/INT3 Serial I/O PPG 0/1 Input Capture 0 External Interrupt INT4/INT5 Input Capture 1 PPG 2/3 External Interrupt INT6/INT7 Watch Timer PPG 4/5 Input Capture 2/3 PPG 6/7 Output Compare 0 Output Compare 1 Input Capture 4/5 Output Compare 2/3 - Input Capture 6/7 16-bit Reload Timer 1 UART 0 RX UART 0 TX UART 1 RX UART 1 TX Flash Memory Delayed interrupt I2OS clear N/A N/A N/A N/A N/A N/A N/A *1 N/A *1 *1 N/A *1 *1 N/A *1 *1 *1 N/A *1 N/A N/A *1 N/A *1 *1 *1 *1 *1 *2 *1 *2 *1 N/A N/A Interrupt vector Number #08 #09 #10 #11 #12 #13 #14 #15 #16 #17 #18 #19 #20 #21 #22 #23 #24 #25 #26 #27 #28 #29 #30 #31 #32 #33 #34 #35 #36 #37 #38 #39 #40 #41 #42 Address FFFFDCH FFFFD8H FFFFD4H FFFFD0H FFFFCCH FFFFC8H FFFFC4H FFFFC0H FFFFBCH FFFFB8H FFFFB4H FFFFB0H FFFFACH FFFFA8H FFFFA4H FFFFA0H FFFF9CH FFFF98H FFFF94H FFFF90H FFFF8CH FFFF88H FFFF84H FFFF80H FFFF7CH FFFF78H FFFF74H FFFF70H FFFF6CH FFFF68H FFFF64H FFFF60H FFFF5CH FFFF58H FFFF54H Interrupt control register Number ICR00 ICR01 ICR02 ICR03 ICR04 ICR05 ICR06 ICR07 ICR08 ICR09 ICR10 ICR11 ICR12 ICR13 ICR14 ICR15 Address 0000B0H 0000B1H 0000B2H 0000B3H 0000B4H 0000B5H 0000B6H 0000B7H 0000B8H 0000B9H 0000BAH 0000BBH 0000BCH 0000BDH 0000BEH 0000BFH 31
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MB90540/545 Series
*1: The interrupt request flag is cleared by the I2OS interrupt clear signal. *2: The interrupt request flag is cleared by the I2OS interrupt clear signal. A stop request is available. N/A:The interrupt request flag is not cleared by the I2OS interrupt clear signal. Note: For a peripheral module with two interrupt causes for a single interrupt number, both interrupt request flags are cleared by the I2OS interrupt clear signal. Note: At the end of I2OS, the I2OS clear signal will be asserted for all the interrupt flags assigned to the same interrupt number. If one interrupt flag starts the I2OS and in the meantime another interrupt flag is set by hardware event, the later event is lost because the flag is cleared by the I2OS clear signal caused by the first event. So it is recommended not to use the I2OS for this interrupt number. Note: If I2OS is enabled, I2OS is initiated when one of the two interrupt signals in the same interrupt control register (ICR) is asserted. This means that different interrupt sources share the same I2OS Descriptor which should be unique for each interrupt source. For this reason, when one interrupt source uses the I2OS, the other interrupt should be disabled.
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s ELECTRICAL CHARACTERISTICS
1. Absolute Maximum Ratings
Value Min. Max. VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 VSS - 0.3 VSS + 6.0 - 2.0 -40 -55 2.0 15 4 100 50 -15 -4 -100 -50 500 400 +85 +150 (VSS = AVSS = 0V) Units V V V V V mA mA mA mA mA mA mA mA mA mW mW C C Average value over a period of 100ms MB90F543/F549 MB90543/549 Average value over a period of 100ms Average value over a period of 100ms Average value over a period of 100ms VCC = AVCC AVCC AVR , AVR+ AVR- *2 *2 *1 Remarks
Parameter
Symbol VCC
Power supply voltage Input voltage Output voltage Clamp Current "L" level max. output current "L" level avg. output current "L" level max. overall output current "L" level avg. overall output current "H" level max. output current "H" level avg. output current "H" level max. overall output current "H" level avg. overall output current Power consumption Operating temperature Storage temperature
AVCC AVR VI VO ICLAMP IOL IOLAV IOL IOLAV IOH IOHAV IOH IOHAV PD TA TSTG
*1: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *2: VI and VO should not exceed VCC + 0.3V. VI should not exceed the specified ratings. However if the maximum current to/from a input is limited by some means with external components, the II rating supercedes the VI rating.
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2. Recommended Conditions
Value Min. 4.5 0.8 VCC VCC - 0.3 VSS - 0.3 VSS - 0.3 0.022 -40 0.1 Typ. 5.0 Max. 5.5 VCC + 0.3 VCC + 0.3 0.2 VCC VSS + 0.3 1.0 +85 (VSS = AVSS = 0V) Units V V V V V F C CMOS hysteresis input pin MD input pin CMOS hysteresis input pin MD input pin Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor. Remarks
Parameter Power supply voltage Input H voltage Input L voltage
Symbol VCC VIHS VIHM VILS VILM
Smooth capacitor
CS
Operating temperature
TA
* C Pin Connection Diagram
C CS
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MB90540/545 Series
3. DC Characteristics
Parameter Symbol Output H voltage Output L voltage Input leak current Pin Condition (VCC = 5.0 V10%, VSS = AVSS = 0V, TA = -40 C to +85 C) Value Units Remarks Min. Typ. Max. VCC - 0.5 -- -- V
VOH
All VCC = 4.5V, output IOH = -4.0mA pins All VCC = 4.5V, output IOL = 4.0mA pins VCC = 5.5V, VSS < VI < VCC VCC = 5.0 V10%, Internal frequency: 16 MHz, At normal operating VCC = 5.0V10%, Internal frequency: 16 MHz, At sleep VCC = 5.0V, Internal frequency: 8 kHz, At sub operation VCC VCC = 5.0V, Internal frequency: 8 kHz, At sub sleep VCC = 5.0V, Internal frequency: 8 kHz, At watch mode VCC = 5.0 V10%, At stop, TA = 25C VCC = 5.0 V10%, At hardware standby mode, TA = 25C Other than AVCC, AVSS, AVR+, AVR-, C, VCC, VSS
VOL
--
--
0.4
V A mA mA mA mA mA mA A A A A A A A A MB90543/549 MB90F543/F549 MB90543/549 MB90F543/F549 MB90543/549 MB90F543/F549 MB90543/549 MB90F543/F549 MB90543/549 MB90F543/F549 MB90543/549 MB90F543/F549 MB90543/549 MB90F543/F549
IIL
-5 -- -- -- -- -- -- -- -- -- -- -- -- -- --
-- TBD 45 TBD 13 TBD 0.2 TBD 10 TBD 10 TBD 5 TBD 50
5 TBD 60 TBD 22 TBD 1 TBD 50 TBD 50 TBD 20 TBD 100
ICC
ICCS
ICCL Power supply current*
ICCLS
ICCT
ICCH1
ICCH2
Input capacity
CIN
--
--
10
80
pF
*: Current values are tentative. They are subject to change without notice according to improvements in the characteristics. The power supply current testing conditions are when using the external clock.
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4. AC Characteristics
(1) Clock Timing (VCC = 5.0 V10%, VSS = AVSS = 0 V, TA = -40 C to +85 C) Value Units Remarks Min. Typ. Max. 3 -- 62.5 -- -- 10 -- -- 1.5 -- 62.5 -- -- 32.768 -- 30.5 -- -- 15.2 -- -- 8.192 -- 122.1 16 -- 333 -- 5 -- -- 5 16 -- 666 -- MHz kHz ns s % ns s ns Duty ratio is about 30 to 70%. When using external clock
Parameter Oscillation frequency Oscillation cycle time Frequency deviation with PLL * Input clock pulse width Input clock rise and fall time Machine clock frequency Machine clock cycle time
Symbol fC fCL tCYL tLCYL f PWH, PWL PWLH,PWLL tCR, tCF fCP fLCP tCP tLCP
Pin X0, X1 X0A, X1A X0, X1 X0A, X1A -- X0 X0A X0 -- -- -- --
MHz When using main clock kHz ns s When using sub-clock When using main clock When using sub-clock
* : Frequency deviation indicates the maximum frequency difference from the target frequency when using a multiplied clock. f = ----- x 100% fo
+ Central frequency fO -
* Clock Timing tCYL 0.8 VCC X0 PWH tCF tLCYL 0.8 VCC X0A PWLH tCF 36 PWLL tCR 0.2 VCC PWL tCR 0.2 VCC
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* Guaranteed operation range 5.5 4.5 Power supply voltage VCC (V)
Guaranteed operation range for MB90F543/F549
3.3 3.0
Guaranteed operation range of MB90543/549 and MB90V540
1.5
3
8 12 Machine clock fCP (MHz)
TB D
Guaranteed PLL operation range
16
* Ocsillation clock frequency and Machine clock frequency 16 12 Machine clock fCP (MHz) 9 8 x1/2 (PLL off) x4 x3 x2 x1
4
3
4
8 Oscillation clock fC (MHz)
16
AC characteristics are set to the measured reference voltage values below. * Input signal waveform Hysteresis Input Pin
0.8 VCC 0.2 VCC
* Output signal waveform Output Pin
2.4 V 0.8 V
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(2) Clock Output Timing (VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin Condition Units Remarks Min. Max. CLK VCC = 5 V10% 62.5 20 -- -- ns ns
Parameter Cycle time CLK CLK
Symbol tCYC tCHCL
tCYC tCHCL CLK 2.4 V 0.8 V 2.4 V
(3) Reset and Hardware Standby Input
Parameter Reset input time
Symbol tRSTL
(VCC = 5.0 V 10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Pin Units Remarks Min. Max. RST 16 tCP -- ns
Hardware standby input time tHSTL HST 16 tCP -- ns "tcp" represents one cycle time of the machine clock. Any reset can not fully initialize the Flash Memory if it is performing the automatic algorithm.
tRSTL, tHSTL RST HST
0.2 VCC
0.2 VCC
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(4) Power On Reset (VCC = 5.0 V10%, VSS = AVSS = 0.0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 0.05 50 30 -- ms ms Due to repetitive operation
Parameter Power on rise time Power off time
Symbol tR tOFF
Pin VCC VCC
tR
VCC 0.2 V
3.5 V 0.2 V tOFF If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 mV/sec, you can operate while using the PLL clock. 0.2 V
VCC TBD Holds RAM data VSS We recommend a rise of 50 mV/ms maximum.
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(5) Bus Timing (Read) (VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. tCP/2 - 20 tCP/2 - 20 -- ns
Parameter ALE pulse width Valid address ALE time
Symbol tLHLL ALE
Pin
tAVLL
ALE, A23 to A16, AD15 to AD00 ALE, AD15 to AD00 A23 toA16, AD15 to AD00, RD A23 to A16, AD15 to AD00 RD RD, AD15 to AD00 RD, AD15 to AD00 RD, ALE RD, A23 to A16 A23 to A16, AD15 to AD00, CLK RD, CLK ALE, RD --
ns
ALE Address valid time Valid address RD time Valid address Valid data input RD pulse width RD Valid data input RD Data hold time RD ALE time RD Address valid time Valid address CLK time RD CLK time ALE RD time
tLLAX
tCP/2 - 15 tCP - 15
--
ns
tAVRL
--
ns
tAVDV tRLRH tRLDV tRHDX tRHLH tRHAX
-- 3 tCP/2 - 20 -- 0 tCP/2 - 15 tCP/2 - 10 tCP/2 - 20 tCP/2 - 20 tCP/2 - 15
5 tCP/2 - 60 -- 3 tCP/2 - 60 -- -- --
ns ns ns ns ns ns
tAVCH tRLCH tLLRL
-- -- --
ns ns ns
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* Bus Timing (Read) tAVCH CLK
2.4 V
tRLCH
2.4 V
tAVLL ALE
2.4 V
tLLAX
2.4 V 0.8 V
tRHLH
2.4 V
tLHLL tAVRL RD
tRLRH
2.4 V 0.8 V
tLLRL tRHAX A23 to A16
2.4 V 0.8 V 2.4 V 0.8 V
tAVDV AD15 to AD00
2.4 V 0.8 V
tRLDV
2.4 V 0.8 V 0.8 VCC 0.2 VCC
tRHDX Read data
0.8 VCC 0.2 VCC
Address
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(6) Bus Timing (Write) (VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. tCP - 15 3 tCP/2 - 20 3 tCP/2 - 20 -- 20 tCP/2 - 10 tCP/2 - 15 tCP/2 - 20 -- -- -- -- ns ns ns ns -- -- -- ns ns ns
Parameter
Symbol
Pin
Valid address WR time WR pulse width Valid data output WR time WR Data hold time WR Address valid time WR ALE time WR CLK time
tAVWL tWLWH tDVWH tWHDX tWHAX tWHLH tWLCH
A23 to A16, AD15 to AD00, WR WR AD15 to AD00, WR AD15 to AD00, WR A23 to A16, WR WR, ALE WR, CLK
* Bus Timing (Write) tWLCH CLK
2.4 V
tWHLH ALE tAVWL WR (WRL, WRH)
0.8 V 2.4 V
tWLWH
2.4 V
tWHAX A23 to A16
2.4 V 0.8 V 2.4 V 0.8 V
tDVWH AD15 to AD00
2.4 V 0.8 V
tWHDX
2.4 V 0.8 V
Address
2.4 V 0.8 V
Write data
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(7) Ready Input Timing (VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 45 0 -- -- ns ns
Parameter RDY setup time RDY hold time
Symbol tRYHS tRYHH
Pin RDY RDY
Note: If the RDY setup time is insufficient, use the auto-ready function.
* Ready Input Timing
CLK
2.4 V
ALE
RD/WR tRYHS RDY no WAIT is used. 0.8 VCC tRYHH 0.8 VCC
RDY When WAIT is used (1 cycle).
0.2 VCC
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(8) Hold Timing (VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 30 tCP tCP 2 tCP ns ns
Parameter Pin floating HAK time HAK time Pin valid time
Symbol tXHAL tHAHV
Pin HAK HAK
Note: There is more than 1 cycle from when HRQ reads in until the HAK is changed.
* Hold Timing HAK tXHAL Each pin 2.4 V 0.8 V High impedance 2.4 V 0.8 V tHAHV 2.4 V 0.8 V
(9) UART0/1, Serial I/O Timing
Parameter Serial clock cycle time SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Serial clock "H" pulse width Serial clock "L" pulse width SCK SOT delay time Valid SIN SCK SCK Valid SIN hold time Note:
Symbol tSCYC tSLOV tIVSH tSHIX tSHSL tSLSH tSLOV tIVSH tSHIX
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Pin Symbol Condition Units Remarks Min. Max. SCK0 to SCK2 SCK0 to SCK2, SOT0 to SOT2 Internal clock operaSCK0 to SCK2, tion output pins are CL = 80 pF + 1 TTL. SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 SCK0 to SCK2 SCK0 to SCK2 SCK0 to SCK2, External clock operSOT0 to SOT2 ation output pins are SCK0 to SCK2, CL = 80 pF + 1 TTL. SIN0 to SIN2 SCK0 to SCK2, SIN0 to SIN2 8 tCP -80 100 60 4 tCP 4 tCP -- 60 60 -- 80 -- -- -- -- 150 -- -- ns ns ns ns ns ns ns ns ns
1. AC characteristic in CLK synchronized mode. 2. CL is load capacity value of pins when testing. 3. tCP is the machine cycle (Unit: ns).
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* Internal Shift Clock Mode tSCYC SCK 2.4 V 0.8 V tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC 0.8 V
* External Shift Clock Mode tSLSH SCK 0.2 VCC 0.2 VCC tSLOV SOT 2.4 V 0.8 V tIVSH SIN 0.8 VCC 0.2 VCC tSHIX 0.8 VCC 0.2 VCC tSHSL 0.8 VCC 0.8 VCC
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(10) Timer Related Resource Input Timing (VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 4 tCP -- ns
Parameter Input pulse width
Symbol tTIWH tTIWL
Pin TIN0, TIN1 IN0 to IN7
* Timer Input Timing
0.8 VCC tTIWH
0.8 VCC 0.2 VCC tTIWL 0.2 VCC
(11) Timer Related Resource Output Timing
Parameter CLK TOUT change time
Symbol tTO
Pin TOT0 to TOT1, PPG0 to PPG3
(VCC = 4.5 V to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 30 -- ns
* Timer Output Timing CLK 2.4 V
TOUT
2.4 V 0.8 V tTO
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(12) Trigger Input Timing (VCC = 4.5 to 5.5 V, VSS = 0 V, TA = -40 C to +85 C) Value Condition Units Remarks Min. Max. -- 5 tCP -- ns
Parameter Input pulse width
Symbol tTRGH tTRGL
Pin INT0 to INT7, ADTG
* Trigger Input Timing
0.8 VCC tTRGH
0.8 VCC 0.2 VCC tTRGL 0.2 VCC
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5. A/D Converter
Parameter Resolution Conversion error Nonlinearity error Differential nonlinearity error Zero reading voltage Full scale reading voltage Conversion time Sampling time Analog port input current Analog input voltage range Reference voltage range Power supply current Reference voltage current Offset between input channels ( VCC = AVCC = 5.0 V10%, VSS = AVSS = 0 V,3.0 V AVR+ - AVR-, TA = -40 C to +85 C) Rated Value Symbol Pin Units Remarks Min. Typ. Max. -- -- -- -- VOT VFST -- -- IAIN VAIN -- -- IA IAH IR IRH -- -- -- -- -- -- -- -- -- -- -- -- 10 5.0 2.5 1.9 bit LSB LSB LSB mV mV ns ns A V V V mA A A A LSB *1 *1
AN0 to AN7 AVR- - 3.5 AVR- + 0.5 AVR- + 4.5 AN0 to AN7 AVR+ - 6.5 AVR+ - 1.5 AVR+ + 1.5 -- -- AN0 to AN7 AN0 to AN7 AVR+ AVR- AVCC AVCC AVR+ AVR+ AN0 to AN7 -- -- -10 AVR- AVR- + 2.7 0 -- -- 200 -- -- 352tCP 64tCP -- -- -- -- 5 -- 400 -- -- -- -- 10 AVR+ AVCC AVR+ - 2.7 -- 5 600 5 4
*1: When not operating A/D converter, this is the current (VCC = AVCC = AVR+ = 5.0 V) when the CPU is stopped.
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6. A/D Converter Glossary
Resolution: Analog changes that are identifiable with the A/D converter Linearity error: The deviation of the straight line connecting the zero transition point ("00 0000 0000" "00 0000 0001") with the full-scale transition point ("11 1111 1110" "11 1111 1111") from actual conversion characteristics Differential linearity error: The deviation of input voltage needed to change the output code by 1 LSB from the theoretical value Total error: The total error is defined as a difference between the actual value and the theoretical value, which includes zero-transition error/full-scale transition error and linearity error.
Total error 3FF 3FE 3FD Actual conversion value 0.5 LSB
{1 LSB x (N - 1) + 0.5 LSB}
Digital output
004 003 002 001
VNT (mesured value) Actual conversion characteristics Theoretical characteristics 0.5 LSB AVR - Analog input AVR + VNT - {1 LSB x (N - 1) + 0.5 LSB} 1 LSB
1 LSB = (Theoretical value)
AVR + - AVR - 1024
[V]
Total error for digital output N =
[LSB]
VOT (Theoretical value) = AVR - + 0.5 LSB[V] VFST (Theoretical value) = AVR + - 1.5 LSB[V]
VNT: Voltage at a transition of digital output from (N - 1) to N
(Continued)
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(Continued)
Linearity error 3FF 3FE 3FD Actual conversion value {1 LSB x (N - 1)+ VOT} VFST (mesured value) N+1 Actual conversion value Differential linearity error Theoretical characteristics
Digital output
Digital output
N
VNT 004 003 002 001 Theoretical characteristics VOT (mesured value) AVR - Analog input AVR + Actual conversion characteristics
N-1
V(N + 1)T (mesured value) VNT (mesured value)
N-2
Actual conversion value
AVR -
Analog input
AVR +
VNT - {1 LSB x (N - 1) + VOT} Linearity error of [LSB] digital output N = 1 LSB Differential linearity error = of digital N 1 LSB = VFST - VOT V(N + 1)T - VNT 1 LSB - 1 LSB [LSB]
[V] 1022 VOT: Voltage at transition of digital output from "000H" to "001H" VFST: Voltage at transition of digital output from "3FEH" to "3FFH"
7. Notes on Using A/D Converter
Select the output impedance value for the external circuit of analog input according to the following conditions. Output impedance values of the external circuit of 15 k or lower are recommended. When capacitors are connected to external pins, the capacitance of several thousand times the internal capacitor value is recommended to minimized the effect of voltage distribution between the external capacitor and internal capacitor. When the output impedance of the external circuit is too high, the sampling period for analog voltages may not be sufficient (sampling period = 4.00 s @machine clock of 16 MHz). * Equipment of analog input circuit model
Analog input C0 Comparator C1
Note: Listed values must be considered as standards. * Error The smaller the | AVR + - AVR - |, the greater the error would become relatively. 50
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MB90540/545 Series
s INSTRUCTIONS (340 INSTRUCTIONS)
Table 1 Item Mnemonic Explanation of Items in Tables of Instructions Meaning
Upper-case letters and symbols: Represented as they appear in assembler. Lower-case letters: Replaced when described in assembler. Numbers after lower-case letters: Indicate the bit width within the instruction code. Indicates the number of bytes. Indicates the number of cycles. m : When branching n : When not branching See Table 4 for details about meanings of other letters in items. Indicates the number of accesses to the register during execution of the instruction. It is used calculate a correction value for intermittent operation of CPU. Indicates the correction value for calculating the number of actual cycles during execution of the instruction. (Table 5) The number of actual cycles during execution of the instruction is the correction value summed with the value in the "~" column. Indicates the operation of instruction. Indicates special operations involving the upper 8 bits of the lower 16 bits of the accumulator. Z : Transfers "0". X : Extends with a sign before transferring. - : Transfers nothing. Indicates special operations involving the upper 16 bits in the accumulator. * : Transfers from AL to AH. - : No transfer. Z : Transfers 00H to AH. X : Transfers 00H or FFH to AH by signing and extending AL. Indicates the status of each of the following flags: I (interrupt enable), S (stack), T (sticky bit), N (negative), Z (zero), V (overflow), and C (carry). * : Changes due to execution of instruction. - : No change. S : Set by execution of instruction. R : Reset by execution of instruction.
# ~
RG B
Operation LH
AH
Indicates whether the instruction is a read-modify-write instruction. (a single instruction that reads data from memory, etc., processes the data, and then writes the result to memory.) * : Instruction is a read-modify-write instruction. - : Instruction is not a read-modify-write instruction. Note: A read-modify-write instruction cannot be used on addresses that have different meanings depending on whether they are read or written. * Number of execution cycles The number of cycles required for instruction execution is acquired by adding the number of cycles for each instruction, a corrective value depending on the condition, and the number of cycles required for program fetch. Whenever the instruction being executed exceeds the two-byte (word) boundary, a program on an internal ROM connected to a 16-bit bus is fetched. If data access is interfered with, therefore, the number of execution cycles is increased. For each byte of the instruction being executed, a program on a memory connected to an 8-bit external data bus is fetched. If data access in interfered with, therefore, the number of execution cycles is increased. When a general-purpose register, an internal ROM, an internal RAM, an internal I/O device, or an external bus is accessed during intermittent CPU operation, the CPU clock is suspended by the number of cycles specified by the CG1/0 bit of the low-power consumption mode control register. When determining the number of cycles required for instruction execution during intermittent CPU operation, therefore, add the value of the number of times access is done x the number of cycles suspended as the corrective value to the number of ordinary execution cycles. 51
I S T N Z V C RMW
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Table 2 Symbol A Explanation of Symbols in Tables of Instructions Meaning 32-bit accumulator The bit length varies according to the instruction. Byte : Lower 8 bits of AL Word : 16 bits of AL Long : 32 bits of AL and AH Upper 16 bits of A Lower 16 bits of A Stack pointer (USP or SSP) Program counter Program bank register Data bank register Additional data bank register System stack bank register User stack bank register Current stack bank register (SSB or USB) Direct page register DTB, ADB, SSB, USB, DPR, PCB, SPB DTB, ADB, SSB, USB, DPR, SPB R0, R1, R2, R3, R4, R5, R6, R7 RW0, RW1, RW2, RW3, RW4, RW5, RW6, RW7 RW0, RW1, RW2, RW3 RL0, RL1, RL2, RL3 Compact direct addressing Direct addressing Physical direct addressing Bit 0 to bit 15 of addr24 Bit 16 to bit 23 of addr24 I/O area (000000H to 0000FFH) 4-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 16-bit data signed and extended from 8-bit immediate data 8-bit displacement 16-bit displacement Bit offset Vector number (0 to 15) Vector number (0 to 255) Bit address PC relative addressing Effective addressing (codes 00 to 07) Effective addressing (codes 08 to 1F) Register list
AH AL SP PC PCB DTB ADB SSB USB SPB DPR brg1 brg2 Ri RWi RWj RLi dir addr16 addr24 ad24 0 to 15 ad24 16 to 23 io imm4 imm8 imm16 imm32 ext (imm8) disp8 disp16 bp vct4 vct8 ( )b rel ear eam rlst
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Table 3 Code 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F R0 R1 R2 R3 R4 R5 R6 R7 Notation RW0 RW1 RW2 RW3 RW4 RW5 RW6 RW7 RL0 (RL0) RL1 (RL1) RL2 (RL2) RL3 (RL3) Effective Address Fields Address format Register direct "ea" corresponds to byte, word, and long-word types, starting from the left Number of bytes in address extension *
--
@RW0 @RW1 @RW2 @RW3 @RW0 + @RW1 + @RW2 + @RW3 + @RW0 + disp8 @RW1 + disp8 @RW2 + disp8 @RW3 + disp8 @RW4 + disp8 @RW5 + disp8 @RW6 + disp8 @RW7 + disp8 @RW0 + disp16 @RW1 + disp16 @RW2 + disp16 @RW3 + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16
Register indirect 0 Register indirect with post-increment 0 Register indirect with 8-bit displacement 1
Register indirect with 16-bit displacement
2 0 0 2 2
Register indirect with index Register indirect with index PC indirect with 16-bit displacement Direct address
Note : The number of bytes in the address extension is indicated by the "+" symbol in the "#" (number of bytes) column in the tables of instructions.
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Table 4 Code Number of Execution Cycles for Each Type of Addressing (a) Operand Ri RWi RLi @RWj @RWj + @RWi + disp8 @RWj + disp16 @RW0 + RW7 @RW1 + RW7 @PC + disp16 addr16 Number of execution cycles for each type of addressing Listed in tables of instructions 2 4 2 2 4 4 2 1 Number of register accesses for each type of addressing
00 to 07 08 to 0B 0C to 0F 10 to 17 18 to 1B 1C 1D 1E 1F
Listed in tables of instructions 1 2 1 1 2 2 0 0
Note : "(a)" is used in the "~" (number of states) column and column B (correction value) in the tables of instructions. Table 5 Compensation Values for Number of Cycles Used to Calculate Number of Actual Cycles Operand Internal register Internal memory even address Internal memory odd address Even address on external data bus (16 bits) Odd address on external data bus (16 bits) External data bus (8 bits) (b) byte
Cycles Access
(c) word
Cycles Access
(d) long
Cycles Access
+0 +0 +0 +1 +1 +1
1 1 1 1 1 1
+0 +0 +2 +1 +4 +4
1 1 2 1 2 2
+0 +0 +4 +2 +8 +8
2 2 4 2 4 4
Notes: * "(b)", "(c)", and "(d)" are used in the "~" (number of states) column and column B (correction value) in the tables of instructions. * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. Table 6 Correction Values for Number of Cycles Used to Calculate Number of Program Fetch Cycles Instruction Internal memory External data bus (16 bits) External data bus (8 bits) Byte boundary -- -- +3 Word boundary +2 +3 --
Notes: * When the external data bus is used, it is necessary to add in the number of wait cycles used for ready input and automatic ready. * Because instruction execution is not slowed down by all program fetches in actuality, these correction values should be used for "worst case" calculations.
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Table 7 Mnemonic MOV MOV MOV MOV MOV MOV MOV MOV MOV MOVN MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOVX MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV /MOV XCH XCH XCH XCH A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A, @RLi+disp8 A, #imm4 A, dir A, addr16 A, Ri A, ear A, eam A, io A, #imm8 A, @A A,@RWi+disp8 A, @RLi+disp8 dir, A addr16, A Ri, A ear, A eam, A io, A @RLi+disp8, A Ri, ear Ri, eam ear, Ri eam, Ri Ri, #imm8 io, #imm8 dir, #imm8 ear, #imm8 eam, #imm8 @AL, AH @A, T A, ear A, eam Ri, ear Ri, eam # ~ Transfer Instructions (Byte) [41 Instructions]
RG
B (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2x (b) 0 2x (b)
Operation byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RLi)+disp8) byte (A) imm4 byte (A) (dir) byte (A) (addr16) byte (A) (Ri) byte (A) (ear) byte (A) (eam) byte (A) (io) byte (A) imm8 byte (A) ((A)) byte (A) ((RWi)+disp8) byte (A) ((RLi)+disp8) byte (dir) (A) byte (addr16) (A) byte (Ri) (A) byte (ear) (A) byte (eam) (A) byte (io) (A) byte ((RLi) +disp8) (A) byte (Ri) (ear) byte (Ri) (eam) byte (ear) (Ri) byte (eam) (Ri) byte (Ri) imm8 byte (io) imm8 byte (dir) imm8 byte (ear) imm8 byte (eam) imm8 byte ((A)) (AH) byte (A) (ear) byte (A) (eam) byte (Ri) (ear) byte (Ri) (eam)
LH AH
I
S
T
N
Z
V
C
RMW
3 2 4 3 2 1 2 2 2+ 3+ (a) 3 2 2 2 3 2 10 3 1 1 3 2 4 3 2 2 2 2 2+ 3+ (a) 3 2 2 2 3 2 5 2 10 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 3 4 2 2 3+ (a) 3 10 3 4+ (a) 4 5+ (a) 2 5 5 2 4+ (a) 3
0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2
Z Z Z Z Z Z Z Z Z Z
* * * * * * * - * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
-* -* -* -* -* -* -* -* -* -R - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
X* X* X* X* X* X* X* X- X* X* - - - - - - - - - - - - - - - - - Z Z - - - - - - - - - - - - - - - - - - - - - - -
4 2 2+ 5+ (a) 7 2 2+ 9+ (a)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 8 Mnemonic MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW MOVW A, dir A, addr16 A, SP A, RWi A, ear A, eam A, io A, @A A, #imm16 A, @RWi+disp8 A, @RLi+disp8 # Transfer Instructions (Word/Long Word) [38 Instructions] ~
RG
B (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) (0) (c) 0 (c) 0 (c) 0 (c) (c)
Operation word (A) (dir) word (A) (addr16) word (A) (SP) word (A) (RWi) word (A) (ear) word (A) (eam) word (A) (io) word (A) ((A)) word (A) imm16
LH AH
I
S
T
N
Z
V
C
RMW
2 3 3 4 1 1 1 2 2 2 2+ 3+ (a) 2 3 2 3 3 2 2 5 3 10 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 3 4 1 2 2 3+ (a) 3 5 10 3 4+ (a) 4 5+ (a) 2 5 2 4+ (a) 3
0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0
- - - - - - - - - word (A) ((RWi) +disp8) - word (A) ((RLi) +disp8) - word (dir) (A) word (addr16) (A) word (SP) (A) word (RWi) (A) word (ear) (A) word (eam) (A) word (io) (A) - - - - - - - word ((RWi) +disp8) (A) - word ((RLi) +disp8) (A) - word (RWi) (ear) - word (RWi) (eam) - word (ear) (RWi) - word (eam) (RWi) - word (RWi) imm16 - word (io) imm16 - word (ear) imm16 - word (eam) imm16 - word ((A)) (AH) word (A) (ear) word (A) (eam) word (RWi) (ear) word (RWi) (eam) long (A) (ear) long (A) (eam) long (A) imm32 long (ear) (A) long (eam) (A) - - - - - - - - - -
* * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * *
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVW dir, A MOVW addr16, A MOVW SP A , MOVW RWi, A MOVW ear, A MOVW eam, A MOVW io, A MOVW @RWi+disp8, A MOVW @RLi+disp8, A MOVW RWi, ear MOVW RWi, eam MOVW ear, RWi MOVW eam, RWi MOVW RWi, #imm16 MOVW io, #imm16 MOVW ear, #imm16 MOVW eam, #imm16 MOVW @AL, AH /MOVW@A, T XCHW XCHW XCHW XCHW A, ear A, eam RWi, ear RWi, eam
2 4 2+ 5+ (a) 2 7 2+ 9+ (a) 2 4 2+ 5+ (a) 5 3 2 4 2+ 5+ (a)
2 0 0 2x (c) 4 0 2 2x (c) 2 0 0 2 0 0 (d) 0 0 (d)
MOVL A, ear MOVL A, eam MOVL A, #imm32 MOVL ear, A MOVL eam, A
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 9 Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDDC SUB SUB SUB SUB SUB SUB SUBC SUBC SUBC SUBDC A,#imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A A, #imm8 A, dir A, ear A, eam ear, A eam, A A A, ear A, eam A Addition and Subtraction Instructions (Byte/Word/Long Word) [42 Instructions] # 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ ~ 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 5 3 4+ (a) 3 5+ (a) 2 3 4+ (a) 3 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a) 2 3 4+ (a) 2 3 5+ (a) 3 4+ (a)
RG
B 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 (b) 0 (b) 0 2x (b) 0 0 (b) 0 0 0 (c) 0 0 2x (c) 0 (c) 0 0 (c) 0 0 2x (c) 0 (c) 0 (d) 0 0 (d) 0
Operation byte (A) (A) +imm8 byte (A) (A) +(dir) byte (A) (A) +(ear) byte (A) (A) +(eam) byte (ear) (ear) + (A) byte (eam) (eam) + (A) byte (A) (AH) + (AL) + (C) byte (A) (A) + (ear) + (C) byte (A) (A) + (eam) + (C)
LH AH
I
S
T
N
Z
V
C
RMW
0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 2 0 0 2 0 0
Z Z Z Z - Z Z Z Z byte (A) (AH) + (AL) + (C) (decimal) Z Z byte (A) (A) -imm8 Z byte (A) (A) - (dir) Z byte (A) (A) - (ear) Z byte (A) (A) - (eam) - byte (ear) (ear) - (A) - byte (eam) (eam) - (A) byte (A) (AH) - (AL) - (C) Z byte (A) (A) - (ear) - (C) Z byte (A) (A) - (eam) - (C) Z byte (A) (AH) - (AL) - (C) (decimal) Z word (A) (AH) + (AL) word (A) (A) +(ear) word (A) (A) +(eam) word (A) (A) +imm16 word (ear) (ear) + (A) word (eam) (eam) + (A) word (A) (A) + (ear) + (C) word (A) (A) + (eam) + (C) word (A) (AH) - (AL) word (A) (A) - (ear) word (A) (A) - (eam) word (A) (A) -imm16 word (ear) (ear) - (A) word (eam) (eam) - (A) word (A) (A) - (ear) - (C) word (A) (A) - (eam) - (C) long (A) (A) + (ear) long (A) (A) + (eam) long (A) (A) +imm32 long (A) (A) - (ear) long (A) (A) - (eam) long (A) (A) -imm32 - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
- - - - - * - - - - - - - - - * - - - - - - - - - * - - - - - - - * - - - - - - - -
ADDW A ADDW A, ear ADDW A, eam ADDW A, #imm16 ADDW ear, A ADDW eam, A ADDCW A, ear ADDCW A, eam SUBW A SUBW A, ear SUBW A, eam SUBW A, #imm16 SUBW ear, A SUBW eam, A SUBCW A, ear SUBCW A, eam ADDL ADDL ADDL SUBL SUBL SUBL
A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4 A, ear 2 6 A, eam 2+ 7+ (a) A, #imm32 5 4
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 10 Mnemonic INC INC DEC DEC INCW INCW ear eam ear eam ear eam Increment and Decrement Instructions (Byte/Word/Long Word) [12 Instructions] # ~
RG
B
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
2 2 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 7 2+ 9+ (a) 2 7 2+ 9+ (a)
2 0 2 0 2 0 2 0 4 0 4 0
0 byte (ear) (ear) +1 2x (b) byte (eam) (eam) +1 0 byte (ear) (ear) -1 2x (b) byte (eam) (eam) -1 0 word (ear) (ear) +1 2x (c) word (eam) (eam) +1 0 word (ear) (ear) -1 2x (c) word (eam) (eam) -1 0 long (ear) (ear) +1 2x (d) long (eam) (eam) +1 0 long (ear) (ear) -1 2x (d) long (eam) (eam) -1
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
- - - - - - - - - - - -
* * * * * * * * * * * *
* * * * * * * * * * * *
* * * * * * * * * * * *
- - - - - - - - - - - -
- * - * - * - * - * - *
DECW ear DECW eam INCL INCL DECL DECL ear eam ear eam
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 11 Mnemonic CMP CMP CMP CMP CMPW CMPW CMPW CMPW CMPL CMPL CMPL A A, ear A, eam A, #imm8 # 1 2 2+ 2 Compare Instructions (Byte/Word/Long Word) [11 Instructions] ~ 1 2 3+ (a) 2 1 2 3+ (a) 2 6 7+ (a) 3
RG
B 0 0 (b) 0 0 0 (c) 0 0 (d) 0
Operation byte (AH) - (AL) byte (A) (ear) byte (A) (eam) byte (A) imm8 word (AH) - (AL) word (A) (ear) word (A) (eam) word (A) imm16 word (A) (ear) word (A) (eam) word (A) imm32
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 0 0 1 0 0 2 0 0
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
* * * * * * * * * * *
- - - - - - - - - - -
A 1 A, ear 2 A, eam 2+ A, #imm16 3 A, ear 2 A, eam 2+ A, #imm32 5
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 12 Mnemonic DIVU DIVU DIVU A A, ear Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 1 2 ~ *
1
RG
B
Operation
Quotient byte (AL) Remainder byte (AH) Quotient byte (A) Remainder byte (ear) Quotient byte (A) Remainder byte (eam) Quotient word (A) Remainder word (ear) Quotient word (A) Remainder word (ear)
LH AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
0 word (AH) /byte (AL) 0 word (A)/byte (ear)
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
- - - - - - - - - - -
* * * * * - - - - - -
* * * * * - - - - - -
- - - - - - - - - - -
*2
A, eam 2+ *3 2 *4
*6 word (A)/byte (eam) 0 long (A)/word (ear)
DIVUW A, ear
DIVUW A, eam 2+ *5 MULU MULU MULU A 1 *8 A, ear 2 *9 A, eam 2+ *10
*7 long (A)/word (eam)
0 0 byte (AH) *byte (AL) word (A) 1 0 byte (A) *byte (ear) word (A) 0 (b) byte (A) *byte (eam) word (A) 0 0 word (AH) *word (AL) long (A) 1 0 word (A) *word (ear) long (A) 0 (c) word (A) *word (eam) long (A)
MULUW A 1 *11 MULUW A, ear 2 *12 MULUW A, eam 2+ *13 *1: *2: *3: *4: *5: *6: *7: *8: *9: *10: *11: *12: *13:
3 when the result is zero, 7 when an overflow occurs, and 15 normally. 4 when the result is zero, 8 when an overflow occurs, and 16 normally. 6 + (a) when the result is zero, 9 + (a) when an overflow occurs, and 19 + (a) normally. 4 when the result is zero, 7 when an overflow occurs, and 22 normally. 6 + (a) when the result is zero, 8 + (a) when an overflow occurs, and 26 + (a) normally. (b) when the result is zero or when an overflow occurs, and 2 x (b) normally. (c) when the result is zero or when an overflow occurs, and 2 x (c) normally. 3 when byte (AH) is zero, and 7 when byte (AH) is not zero. 4 when byte (ear) is zero, and 8 when byte (ear) is not zero. 5 + (a) when byte (eam) is zero, and 9 + (a) when byte (eam) is not 0. 3 when word (AH) is zero, and 11 when word (AH) is not zero. 4 when word (ear) is zero, and 12 when word (ear) is not zero. 5 + (a) when word (eam) is zero, and 13 + (a) when word (eam) is not zero.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 13 Signed Multiplication and Division Instructions (Byte/Word/Long Word) [11 Instructions] # 2 2 ~ *1 *2 *3 *4 *5
RG
Mnemonic DIV DIV DIV DIVW DIVW A A, ear
B 0
Operation
LH
AH
I
S
T
N
Z
V
C
RMW
0 1 0 1 0
A, eam 2 + A, ear A, eam 2 2+
word (AH) /byte (AL) Quotient byte (AL) Remainder byte (AH) 0 word (A)/byte (ear) Quotient byte (A) Remainder byte (ear) *6 word (A)/byte (eam) Quotient byte (A) Remainder byte (eam) 0 long (A)/word (ear) Quotient word (A) Remainder word (ear) *7 long (A)/word (eam) Quotient word (A) Remainder word (eam) 0 0 (b) 0 0 (c) byte (AH) *byte (AL) word (A) byte (A) *byte (ear) word (A) byte (A) *byte (eam) word (A) word (AH) *word (AL) long (A) word (A) *word (ear) long (A) word (A) *word (eam) long (A)
Z Z Z - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
- - - - -
* * * * *
* * * * *
- - - - -
MULU MULU MULU MULUW MULUW MULUW *1: *2: *3: *4:
A 2 A, ear 2 A, eam 2 + A 2 A, ear 2 A, eam 2 +
*8 *9 *10 *11 *12 *13
0 1 0 0 1 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
Set to 3 when the division-by-0, 8 or 18 for an overflow, and 18 for normal operation. Set to 3 when the division-by-0, 10 or 21 for an overflow, and 22 for normal operation. Set to 4 + (a) when the division-by-0, 11 + (a) or 22 + (a) for an overflow, and 23 + (a) for normal operation. Positive dividend: Set to 4 when the division-by-0, 10 or 29 for an overflow, and 30 for normal operation. Negative dividend: Set to 4 when the division-by-0, 11 or 30 for an overflow and 31 for normal operation. *5: Positive dividend: Set to 4 + (a) when the division-by-0, 11 + (a) or 30 + (a) for an overflow, and 31 + (a) for normal operation. Negative dividend: Set to 4 + (a) when the division-by-0, 12 + (a) or 31 + (a) for an overflow, and 32 + (a) for normal operation. *6: When the division-by-0, (b) for an overflow, and 2 x (b) for normal operation. *7: When the division-by-0, (c) for an overflow, and 2 x (c) for normal operation. *8: Set to 3 when byte (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *9: Set to 3 when byte (ear) is zero, 12 when the result is positive, and 13 when the result is negative. *10: Set to 4 + (a) when byte (eam) is zero, 13 + (a) when the result is positive, and 14 + (a) when the result is negative. *11: Set to 3 when word (AH) is zero, 12 when the result is positive, and 13 when the result is negative. *12: Set to 3 when word (ear) is zero, 16 when the result is positive, and 19 when the result is negative. *13: Set to 4 + (a) when word (eam) is zero, 17 + (a) when the result is positive, and 20 + (a) when the result is negative. Notes: * When overflow occurs during DIV or DIVW instruction execution, the number of execution cycles takes two values because of detection before and after an operation. * When overflow occurs during DIV or DIVW instruction execution, the contents of AL are destroyed. * For (a) to (d), refer to "Table 4 Number of Execution Cycles for Effective Address in Addressing Modes" and "Table 5 Correction Values for Number of Cycles for Calculating Actual Number of Cycles."
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Table 14 Mnemonic AND AND AND AND AND OR OR OR OR OR XOR XOR XOR XOR XOR NOT NOT NOT ANDW ANDW ANDW ANDW ANDW ANDW ORW ORW ORW ORW ORW ORW XORW XORW XORW XORW XORW XORW A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A, #imm8 A, ear A, eam ear, A eam, A A ear eam # ~ Logical 1 Instructions (Byte/Word) [39 Instructions]
RG
B 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b) 0 0 (b) 0 2x (b)
Operation byte (A) (A) and imm8 byte (A) (A) and (ear) byte (A) (A) and (eam) byte (ear) (ear) and (A) byte (eam) (eam) and (A) byte (A) (A) or imm8 byte (A) (A) or (ear) byte (A) (A) or (eam) byte (ear) (ear) or (A) byte (eam) (eam) or (A) byte (A) (A) xor imm8 byte (A) (A) xor (ear) byte (A) (A) xor (eam) byte (ear) (ear) xor (A) byte (eam) (eam) xor (A)
LH AH
I
S
T
N
Z
V
C
RMW
2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 2 2 2 3 2+ 4+ (a) 2 3 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - * - - - - * - - - - * - - * - - - - - * - - - - - * - - - - - * - - *
0 byte (A) not (A) 0 byte (ear) not (ear) 2x (b) byte (eam) not (eam) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) 0 0 0 (c) 0 2x (c) word (A) (AH) and (A) word (A) (A) and imm16 word (A) (A) and (ear) word (A) (A) and (eam) word (ear) (ear) and (A) word (eam) (eam) and (A) word (A) (AH) or (A) word (A) (A) or imm16 word (A) (A) or (ear) word (A) (A) or (eam) word (ear) (ear) or (A) word (eam) (eam) or (A) word (A) (AH) xor (A) word (A) (A) xor imm16 word (A) (A) xor (ear) word (A) (A) xor (eam) word (ear) (ear) xor (A) word (eam) (eam) xor (A)
A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) A 1 2 A, #imm16 3 2 A, ear 2 3 A, eam 2+ 4+ (a) ear, A 2 3 eam, A 2+ 5+ (a) 1 2 2 3 2+ 5+ (a)
NOTW A NOTW ear NOTW eam
0 word (A) not (A) 0 word (ear) not (ear) 2x (c) word (eam) not (eam)
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 15 Mnemonic ANDL A, ear ANDL A, eam ORL ORL A, ear A, eam # 2 2+ 2 2+ 2 2+ ~ 6 7+ (a) 6 7+ (a) 6 7+ (a) Logical 2 Instructions (Long Word) [6 Instructions]
RG
B 0 (d) 0 (d) 0 (d)
Operation long (A) (A) and (ear) long (A) (A) and (eam) long (A) (A) or (ear) long (A) (A) or (eam) long (A) (A) xor (ear) long (A) (A) xor (eam)
LH
AH
I
S
T
N
Z
V
C
RMW
2 0 2 0 2 0
- - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
R R R R R R
- - - - - -
- - - - - -
XORL A, ea XORL A, eam
Table 16 Mnemonic NEG NEG NEG A ear eam # 1 ~ 2
Sign Inversion Instructions (Byte/Word) [6 Instructions]
RG
B 0
Operation byte (A) 0 - (A)
LH
AH
I
S
T
N
Z
V
C
RMW
0 2 0 0 2 0
X - - - - -
- - - - - -
- - - - - -
- - - - - -
- - - - - -
* * * * * *
* * * * * *
* * * * * *
* * * * * *
- - * - - *
2 3 2+ 5+ (a) 1 2
0 byte (ear) 0 - (ear) 2x (b) byte (eam) 0 - (eam) 0 word (A) 0 - (A)
NEGW A NEGW ear NEGW eam
2 3 2+ 5+ (a)
0 word (ear) 0 - (ear) 2x (c) word (eam) 0 - (eam)
Table 17 Mnemonic NRML A, R0 # 2 ~ *1 RG 1 B 0
Normalize Instruction (Long Word) [1 Instruction] Operation
LH AH I S T N Z V C RMW
long (A) Shift until first digit is "1" - byte (R0) Current shift count
-
-
-
-
-
*
-
-
-
*1: 4 when the contents of the accumulator are all zeroes, 6 + (R0) in all other cases (shift count). Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 18 Mnemonic
RORC A ROLC A RORC ear RORC eam ROLC ear ROLC eam ASR LSR LSL A, R0 A, R0 A, R0
Shift Instructions (Byte/Word/Long Word) [18 Instructions]
RG
# 2 2
~ 2 2
B 0 0
Operation
byte (A) Right rotation with carry byte (A) Left rotation with carry byte (ear) Right rotation with carry byte (eam) Right rotation with carry byte (ear) Left rotation with carry byte (eam) Left rotation with carry
byte (A) Arithmetic right barrel shift (A, R0) byte (A) Logical right barrel shift (A, R0) byte (A) Logical left barrel shift (A, R0) word (A) Arithmetic right shift (A, 1 bit)
LH AH
I
S
T
N
Z
V
C
RMW
0 0
- - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - -
--- --- - - - - - - - - - - - -
* * * * * * * * *
* * * * * * * * *
- - - - - - - - - - - - - - - - - -
* * * * * * * * * * * * * * * * * *
- - - * - * - - - - - - - - - - - -
2 3 2+ 5+ (a) 2 3 2+ 5+ (a) 2 2 2 1 1 1 2 2 2 2 2 2 *1 *1 *1 2 2 2 *1 *1 *1 *2 *2 *2
2 0 0 2x (b) 2 0 0 2x (b) 1 1 1 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0
--* --* ---
ASRW A LSRW A/SHRW A LSLW A/SHLW A ASRW A, R0 LSRW A, R0 LSLW A, R0 ASRL A, R0 LSRL A, R0 LSLL A, R0
word (A) Logical right shift (A, 1 bit) word (A) Logical left shift (A, 1 bit)
word (A) Arithmetic right barrel shift (A, R0) word (A) Logical right barrel shift (A, R0) word (A) Logical left barrel shift (A, R0) long (A) Logical right barrel shift (A, R0) long (A) Logical left barrel shift (A, R0)
--*** --*R* ---** --* --* --- --* --* --- * * * * * * * * * * * *
long (A) Arithmetic right shift (A, R0) -
- -
*1: 6 when R0 is 0, 5 + (R0) in all other cases. *2: 6 when R0 is 0, 6 + (R0) in all other cases. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 19 Mnemonic BZ/BEQ BNZ/BNE BC/BLO BNC/BHS BN rel BP rel BV rel BNV rel BT rel BNT rel BLT rel BGE rel BLE rel BGT rel BLS rel BHI rel BRA rel JMP JMP JMP JMP JMPP JMPP JMPP CALL CALL CALL CALLV CALLP rel rel rel rel # 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 ~ * *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+ (a) 5 6+ (a) 4 6 7+ (a) 6 7 10
1
Branch 1 Instructions [31 Instructions] B 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 Operation Branch when (Z) = 1 Branch when (Z) = 0 Branch when (C) = 1 Branch when (C) = 0 Branch when (N) = 1 Branch when (N) = 0 Branch when (V) = 1 Branch when (V) = 0 Branch when (T) = 1 Branch when (T) = 0 Branch when (V) xor (N) = 1 Branch when (V) xor (N) = 0
Branch when ((V) xor (N)) or (Z) = 1 Branch when ((V) xor (N)) or (Z) = 0
LH AH I S T N Z V C RMW
RG
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0
Branch when (C) or (Z) = 1 Branch when (C) or (Z) = 0 Branch unconditionally word (PC) (A) word (PC) addr16 word (PC) (ear) word (PC) (eam)
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
@A addr16 @ear @eam @ear *3 @eam *3 addr24
word (PC) (ear), (PCB) (ear +2) word (PC) (eam), (PCB) (eam +2)
2 @ear *4 @eam *4 2+ addr16 *5 3 1 #vct4 *5 2 @ear *6
(c) 2x (c) (c) 2x (c) 2x (c) *2 2x (c)
CALLP @eam *6 CALLP addr24 *7 *1: *2: *3: *4: *5: *6: *7:
2+ 11+ (a) 4 10
word (PC) ad24 0 to 15, (PCB) ad24 16 to 23 word (PC) (ear) word (PC) (eam) word (PC) addr16 Vector call instruction word (PC) (ear) 0 to 15, (PCB) (ear) 16 to 23 word (PC) (eam) 0 to 15, (PCB) (eam) 16 to 23 word (PC) addr0 to 15, (PCB) addr16 to 23
4 when branching, 3 when not branching. (b) + 3 x (c) Read (word) branch address. W: Save (word) to stack; R: read (word) branch address. Save (word) to stack. W: Save (long word) to W stack; R: read (long word) R branch address. Save (long word) to stack.
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 20 Mnemonic CBNE A, #imm8, rel CWBNE A, #imm16, rel CBNE
CBNE
Branch 2 Instructions [19 Instructions] B 0 0 0 (b) 0 (c) 0 Operation
Branch when byte (A) imm8 Branch when word (A) imm16 Branch when byte (ear) imm8 Branch when byte (eam) imm8 Branch when word (ear) imm16 Branch when word (eam) imm16
LH AH I S T N Z V C RMW
# 3 4
10
~ * *1 *2 *3 *4 *3 *5
1
RG
0 0 1 0 1 0 2
- - - - - - - - - - - - - - - -
----* ----* - - - - - - - - - - - - - - - - * * * *
* * * * * * * * * * - - - - *
* * * * * *
* * * * * *
- - - - - - - * - * - - - - - -
ear, #imm8, rel
eam, #imm8, rel*
CWBNE ear, #imm16, rel
CWBNE eam, #imm16, rel*10
4 4+ 5 5+ 3
DBNZ DBNZ
ear, rel eam, rel
3+ *6 3 *5
Branch when byte (ear) = (ear) - 1, and (ear) 0 2 2x (b) Branch when byte (eam) = (eam) - 1, and (eam) 0 2 2 0 0 0 0 0 0 Branch when word (ear) = (ear) - 1, and (ear) 0 2x (c) Branch when word (eam) = (eam) - 1, and (eam) 0 8x (c) 6x (c) 6x (c) 8x (c) *7 (c) Software interrupt Software interrupt Software interrupt Software interrupt Return from interrupt At constant entry, save old frame pointer to stack, set new frame pointer, and allocate local pointer area At constant entry, retrieve old frame pointer from stack. Return from subroutine Return from subroutine 0
----* ----* ----* ----* - - - - - R R R R * S S S S * - - - - * - - - - *
*- *- *- *- - - - - * - - - - *
DWBNZ ear, rel DWBNZ eam, rel INT INT INTP INT9 RETI LINK #vct8 addr16 addr24
3+ *6 2 3 4 1 1 2 20 16 17 20 15 6
#local8
--------
UNLINK RET *8 RETP *9
1 1 1
5 4 6
0 0 0
(c) (c) (d)
- - -
-------- -------- --------
- - -
*1: 5 when branching, 4 when not branching *2: 13 when branching, 12 when not branching *3: 7 + (a) when branching, 6 + (a) when not branching *4: 8 when branching, 7 when not branching *5: 7 when branching, 6 when not branching *6: 8 + (a) when branching, 7 + (a) when not branching *7: Set to 3 x (b) + 2 x (c) when an interrupt request occurs, and 6 x (c) for return. *8: Retrieve (word) from stack *9: Retrieve (long word) from stack *10: In the CBNE/CWBNE instruction, do not use the RWj+ addressing mode. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 21 Mnemonic PUSHW A PUSHW AH PUSHW PS PUSHW rlst POPW POPW POPW POPW JCTX A AH PS rlst @A # 1 1 1 2 1 1 1 2 1 2 2 2 2 Other Control Instructions (Byte/Word/Long Word) [36 Instructions] ~ 4 4 4 *3 3 3 4 *2 14 3 3 2 2
RG
B (c) (c) (c) *4 (c) (c) (c) *4
Operation
word (SP) (SP) -2, ((SP)) (A) word (SP) (SP) -2, ((SP)) (AH) word (SP) (SP) -2, ((SP)) (PS) (SP) (SP) -2n, ((SP)) (rlst) word (A) ((SP)), (SP) (SP) +2 word (AH) ((SP)), (SP) (SP) +2 word (PS) ((SP)), (SP) (SP) +2 (rlst) ((SP)), (SP) (SP) +2n
LH AH
I
S
T
N
Z
V
C
RMW
0 0 0 *5 0 0 0 *5 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0
- - - - - - - - -
- - - - * - - - - - - - - - - * * - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - -
- - - - - - - - - - - - - - - - - - - - - - - - - - - -
------- ------- ******* ------- * * * * * * * * * * * * * * * * * * * * *
6x (c) Context switch instruction 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
AND CCR, #imm8 OR CCR, #imm8 MOV RP #imm8 , MOV ILM, #imm8
byte (CCR) (CCR) and imm8 - - byte (CCR) (CCR) or imm8 byte (RP) imm8 byte (ILM) imm8 word (RWi) ear word (RWi) eam word(A) ear word (A) eam word (SP) (SP) +ext (imm8) word (SP) (SP) +imm16 byte (A) (brgl) byte (brg2) (A) No operation
Prefix code for accessing AD space Prefix code for accessing DT space Prefix code for accessing PC space Prefix code for accessing SP space
- - - - - - - -
------- ------- - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MOVEA RWi, ear 2 3 MOVEA RWi, eam 2+ 2+ (a) MOVEA A, ear 2 1 MOVEA A, eam 2+ 1+ (a) ADDSP #imm8 ADDSP #imm16 MOV MOV NOP ADB DTB PCB SPB NCC CMR A, brgl brg2, A 2 3 2 2 1 1 1 1 1 1 1 3 3 *1 1 1 1 1 1 1 1 1
------- ------- --- --- - - - - - - - - - - - - - - - - - - - - - * * - - - - - - - * * - - - - - - - -- -- - - - - - - - - - - - - - -
Z* -- - - - - - - - - - - - - - -
Prefix code for no flag change
Prefix code for common register bank
*1: PCB, ADB, SSB, USB, and SPB : 1 state DTB, DPR : 2 states *2: 7 + 3 x (pop count) + 2 x (last register number to be popped), 7 when rlst = 0 (no transfer register) *3: 29 + (push count) - 3 x (last register number to be pushed), 8 when rlst = 0 (no transfer register) *4: Pop count x (c), or push count x (c) *5: Pop count or push count. Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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Table 22 Mnemonic MOVB A, dir:bp MOVB A, addr16:bp MOVB A, io:bp MOVB dir:bp, A MOVB addr16:bp, A MOVB io:bp, A SETB dir:bp SETB addr16:bp SETB io:bp CLRB dir:bp CLRB addr16:bp CLRB io:bp BBC BBC BBC BBS BBS BBS dir:bp, rel addr16:bp, rel io:bp, rel dir:bp, rel addr16:bp, rel io:bp, rel # 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 ~ 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4
RG
Bit Manipulation Instructions [21 Instructions] B (b) (b) (b) Operation byte (A) (dir:bp) b byte (A) (addr16:bp) b byte (A) (io:bp) b
LH AH I S T N Z V C RMW
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Z Z Z - - - - - - - - - - - - - - - - - -
* * * - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
* * * * * * - - - - - - - - - - - - - - -
* * * * * * - - - - - - * * * * * * * - -
- - - - - - - - - - - - - - - - - - - - -
- - - - - - - - - - - - - - - - - - - - -
- - - * * * * * * * * * - - - - - - * - -
2x (b) bit (dir:bp) b (A) 2x (b) bit (addr16:bp) b (A) 2x (b) bit (io:bp) b (A) 2x (b) bit (dir:bp) b 1 2x (b) bit (addr16:bp) b 1 2x (b) bit (io:bp) b 1 2x (b) bit (dir:bp) b 0 2x (b) bit (addr16:bp) b 0 2x (b) bit (io:bp) b 0 (b) (b) (b) (b) (b) (b) 2x (b) *5 *5 Branch when (dir:bp) b = 0 Branch when (addr16:bp) b = 0 Branch when (io:bp) b = 0 Branch when (dir:bp) b = 1 Branch when (addr16:bp) b = 1 Branch when (io:bp) b = 1
Branch when (addr16:bp) b = 1, bit = 1
SBBS addr16:bp, rel WBTS io:bp WBTC io:bp *1: *2: *3: *4: *5:
Wait until (io:bp) b = 1 Wait until (io:bp) b = 0
8 when branching, 7 when not branching 7 when branching, 6 when not branching 10 when condition is satisfied, 9 when not satisfied Undefined count Until condition is satisfied
Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles." Table 23 Mnemonic SWAP SWAPW EXT EXTW ZEXT ZEXTW Accumulator Manipulation Instructions (Byte/Word) [6 Instructions] # 1 1 1 1 1 1 ~ 3 2 1 2 1 1
RG
B 0 0 0 0 0 0
Operation byte (A) 0 to 7 (A) 8 to 15 word (AH) (AL) byte sign extension word sign extension byte zero extension word zero extension
LH
AH
I
S
T
N
Z
V
C
RMW
0 0 0 0 0 0
- - X - Z -
- * - X - Z
- - - - - -
- - - - - -
- - - - - -
- - * * R R
- - * * * *
- - - - - -
- - - - - -
- - - - - -
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Table 24 Mnemonic MOVS/MOVSI MOVSD SCEQ/SCEQI SCEQD FISL/FILSI # 2 2 2 2 ~ * *2 *1 *1
2
String Instructions [10 Instructions] Operation
LH AH I S T N Z V C RMW
RG
B * *3 *4 *4 *3 *6 *6 *7 *7 *6
3
* *5 *5 *5
5
Byte transfer @AH+ @AL+, counter = RW0 Byte transfer @AH- @AL-, counter = RW0 Byte retrieval (@AH+) - AL, counter = RW0 Byte retrieval (@AH-) - AL, counter = RW0 Byte filling @AH+ AL, counter = RW0 Word transfer @AH+ @AL+, counter = RW0 Word transfer @AH- @AL-, counter = RW0 Word retrieval (@AH+) - AL, counter = RW0 Word retrieval (@AH-) - AL, counter = RW0 Word filling @AH+ AL, counter = RW0
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - - - - - - - - -
- - * * * - - * * *
- - * * * - - * * *
- - * * - - - * * -
- - * * - - - * * -
- - - - - - - - - -
2 6m +6 *5 *2 *2 *1 *1 *8 *8 *8 *8
MOVSW/MOVSWI 2 MOVSWD 2 SCWEQ/SCWEQI SCWEQD FILSW/FILSWI 2 2
2 6m +6 *8
m: RW0 value (counter value) n: Loop count *1: 5 when RW0 is 0, 4 + 7 x (RW0) for count out, and 7 x n + 5 when match occurs *2: 5 when RW0 is 0, 4 + 8 x (RW0) in any other case *3: (b) x (RW0) + (b) x (RW0) when accessing different areas for the source and destination, calculate (b) separately for each. *4: (b) x n *5: 2 x (RW0) *6: (c) x (RW0) + (c) x (RW0) when accessing different areas for the source and destination, calculate (c) separately for each. *7: (c) x n *8: 2 x (RW0) Note : For an explanation of "(a)" to "(d)", refer to Table 4, "Number of Execution Cycles for Each Type of Addressing," and Table 5, "Correction Values for Number of Cycles Used to Calculate Number of Actual Cycles."
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MB90540/545 Series
s ORDERING INFORMATION
Part number MB90543PF MB90F543PF MB90548PF MB90F548PF MB90543PFF MB90F543PFF MB90548PFF MB90F548PFF MB90V540CR Package 100-pin Plastic QFP (FPT-100P-M06) Remarks
100-pin Plastic LQFP (FPT-100P-M05) 256-pin Ceramic PGA (PGA-256C-A01)
For evaluation
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MB90540/545 Series
s PACKAGE DIMENSIONS
100-pin Plastic QFP (FPT-100P-M06)
23.900.40(.941.016) 20.000.20(.787.008)
80 81 51 50
3.35(.132)MAX (Mounting height) 0.05(.002)MIN (STAND OFF)
14.000.20 (.551.008)
INDEX
100 31
17.900.40 (.705.016)
12.35(.486) REF
16.300.40 (.642.016)
"A" LEAD No.
1 30
0.65(.0256)TYP
0.300.10 (.012.004)
0.13(.005)
M
0.150.05(.006.002)
Details of "A" part 0.25(.010) "B" 0.10(.004) 18.85(.742)REF 22.300.40(.878.016) 0.30(.012) 0.18(.007)MAX 0.53(.021)MAX Details of "B" part
0
10
0.800.20 (.031.008)
C
1994 FUJITSU LIMITED F100008-3C-2
Dimensions in mm (inches)
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MB90540/545 Series
100-pin Plastic LQFP (FPT-100P-M05)
16.000.20(.630.008)SQ
75
1.50 -0.10
51
+0.20 +.008
(Mouting height)
14.000.10(.551.004)SQ
.059 -.004
76
50
12.00 (.472) REF INDEX
15.00 (.591) NOM
Details of "A" part 0.15(.006)
100
26
0.15(.006) 0.15(.006)MAX
LEAD No.
1
25
"B"
+0.05 +.002
"A" 0.50(.0197)TYP 0.18 -0.03 .007
+0.08 +.003 -.001
0.40(.016)MAX 0.127 -0.02 .005 -.001
0.08(.003)
M
Details of "B" part 0.100.10 (STAND OFF) (.004.004)
0.10(.004)
0.500.20(.020.008) 0~10
C
1995 FUJITSU LIMITED F100007S-2C-3
Dimensions in mm (inches)
71
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MB90540/545 Series
250-pin Ceramic PGA (PGA-256C-A01)
C0.51 (.020) TYP (3 PLCS)
0.20 0.05 (.0079 .002)
22.86 (.900) REF
INDEX AREA C1.02 (.040) TYP 25.10 0.30 SQ (.988 .012) 6.35 (.250) MAX
1.27 (.050) TYP 1.50 + 0.30 (.059 + .012 ) - 0.10 - .004 EXTRA INDEX PIN
C
1994 FUJITSU LIMITED R256001SC-5-3
Dimensions in mm (inches)
72
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MB90540/545 Series
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka Nakahara-ku, Kawasaki-shi Kanagawa 211-8588, Japan Tel: 81(44) 754-3763 Fax: 81(44) 754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Law of Japan, the prior authorization by Japanese government will be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. Semiconductor Division 3545 North First Street San Jose, CA 95134-1804, USA Tel: (408) 922-9000 Fax: (408) 922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: (800) 866-8608 Fax: (408) 922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10 D-63303 Dreieich-Buchschlag Germany Tel: (06103) 690-0 Fax: (06103) 690-122
http://www.fujitsu-ede.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan New Tech Park Singapore 556741 Tel: (65) 281-0770 Fax: (65) 281-0220
http://www.fmap.com.sg/
F9909 (c) FUJITSU LIMITED Printed in Japan

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